3D Fan-Out SiP Packaging With Asymmetric Dual-Side Molding
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and miniaturization of electronic components while maintaining cost-effectiveness and performance, particularly in the development of smaller and more complex packaging techniques for semiconductor dies.
Innovation Solution
The implementation of a System-in-Package (SiP) device with an asymmetric dual-sided molded package on a multi-layered Redistribution Layer (RDL) structure, where heterogeneous dies are integrated on opposing sides of a redistribution structure, using a single carrier substrate and different molding compounds to form a high-density, low-cost package with enhanced functionalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but integration density and functionality are limited
Solution Approach 1:
The packaging structure is divided into multiple layers including a carrier substrate, multiple redistribution layers (RDLs) with different patterns, and multiple molding compounds. Each layer performs specific functions: the carrier substrate provides mechanical support, RDLs enable signal routing and fan-out, and molding compounds provide encapsulation and stress relief. This segmentation allows high integration density while maintaining manufacturability through modular processing steps.
Solution Approach 2:
The patent transitions from planar 2D packaging to 3D stacked packaging by integrating multiple RDL layers at different heights and orientations. The first RDL is formed on the carrier substrate, followed by placement of semiconductor dies, then formation of a second RDL on top. This vertical stacking enables higher integration density and functionality without increasing the package footprint, resolving the contradiction between versatility and complexity.
2Adaptability or versatility
If feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the first redistribution layer (RDL) and its associated vias and conductive structures on the carrier substrate before placing the semiconductor dies. This preliminary formation of the interconnect structure establishes precise routing paths and connection points in advance, allowing subsequent die placement and packaging to proceed with relaxed precision requirements. The pre-formed RDL acts as a template that guides the integration process.
Solution Approach 2:
The carrier substrate serves as an intermediary platform that provides mechanical support and houses the first RDL structure. This intermediary layer allows the semiconductor dies to be mounted on a stable, pre-configured interconnect structure rather than requiring direct precision bonding to final interconnects. The carrier substrate absorbs manufacturing tolerances and provides a forgiving platform for die attachment, reducing the overall precision requirements of the packaging process.
3Ease of manufacture
If larger pitch is used for electrical contacts, then manufacturing is easier, but functional density decreases
Solution Approach 1:
The patent employs asymmetric RDL structures where the first RDL and second RDL have different patterns, trace widths, and via configurations optimized for their respective functions. The first RDL on the carrier substrate uses larger pitch traces for robust mechanical connection and signal routing, while the second RDL on top of the dies uses denser patterns for high-density interconnect. This asymmetric design allows each layer to be optimized independently, achieving both ease of manufacture in the carrier substrate and high functional density in the final package.
Solution Approach 2:
The patent implements a nested RDL structure where the second RDL is formed on top of the first RDL and semiconductor dies, with the second RDL traces routing over and alongside the first RDL structures. This nesting allows the package to achieve high functional density by stacking interconnect layers vertically, while the outermost contact pads can maintain larger pitches for ease of manufacturing and assembly. The nested configuration multiplies the effective interconnect capacity without proportionally increasing the package footprint.
4Adaptability or versatility
If heterogeneous dies are integrated on opposing sides, then functionality is enhanced, but structural complexity increases
Solution Approach 1:
The patent integrates different types of semiconductor dies (e.g., logic dies, memory dies, passive devices) at specific locations on the carrier substrate and/or on opposite sides of the package, with each die type positioned to optimize its functional contribution. The RDL structures are locally configured to route signals appropriately to each die type, with specialized interconnect patterns for high-speed logic, dense routing for memory, and simplified connections for passive devices. This local optimization allows heterogeneous integration that enhances functionality while managing complexity through targeted, rather than uniform, design approaches.
Data Source
AI summary
Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.