3D FD-SOI Transistor Stacking for Smaller, Lower-Cost Chips
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Solution Overview
Problem
Current semiconductor processes face challenges in reducing chip size and cost while maintaining performance, particularly with the increasing demands of 5G technology and advanced applications like artificial intelligence and smart cars.
Innovation Solution
A 3D structure with fully depleted silicon-on-insulator (FD-SOI) transistors is developed by stacking wafers, which includes a handler wafer, multiple device layers with FD-SOI transistors, and metal interconnection sets for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If process shrinkage is used to improve product performance, then transmission speed and information transmission capability are improved, but equipment cost increases and technical difficulties rise
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked transistors. Multiple transistor layers are stacked vertically on a single substrate, utilizing the third dimension (height) to increase device density and performance without requiring further shrinkage of the lateral process dimensions.
Solution Approach 2:
The patent combines multiple transistor layers into a single integrated stack structure. The stacked transistor layers share common substrate and interconnection structures, merging multiple devices into one compact unit that achieves high performance without proportionally increasing manufacturing complexity.
2Speed
If process shrinkage is used to improve product performance, then transmission speed and information transmission capability are improved, but equipment cost increases
Solution Approach 1:
The patent achieves performance improvement through vertical stacking in the third dimension rather than lateral shrinkage, allowing existing manufacturing equipment to be used for producing higher-performance devices without requiring more expensive advanced lithography tools.
Solution Approach 2:
The stacked transistor structure allows a single substrate to host multiple functional layers that can be configured for different applications (e.g., logic, memory, RF), making the manufacturing process more versatile and reducing the need for specialized equipment for each application type.
3Speed
If advanced packaging is used to improve performance, then product performance is improved, but chip size increases
Solution Approach 1:
The patent integrates multiple transistor layers vertically within a single chip footprint, achieving advanced functionality and high performance without requiring multiple separate chips to be packaged together. This vertical integration maintains small chip size while delivering advanced performance.
Solution Approach 2:
The stacked transistor layers are nested vertically within each other, with each layer contained within the same lateral footprint. This nesting approach allows multiple functional layers to coexist in a compact volume, avoiding the need for larger packaging solutions.
4Speed
If advanced packaging is used to improve performance, then product performance is improved, but cost increases
Solution Approach 1:
The patent combines multiple transistor layers into a single integrated structure that can be manufactured in one continuous process flow on a single substrate. This merging eliminates the need for separate manufacturing and packaging processes for multiple chips, reducing overall cost while achieving advanced performance.
Solution Approach 2:
By moving to vertical stacking, the patent achieves advanced functionality without requiring complex multi-chip packaging processes, thereby avoiding the cost penalties associated with advanced packaging while still delivering high-performance results.
Data Source
AI summary
A three-dimensional structure with an FD-SOI transistor includes a handler wafer, a first device layer and a second device layer stacked in sequence from bottom to top. The first device layer includes a first SOI layer, a first FD-SOI transistor and a first back gate. The first SOI layer includes a first front side and a first back side. The first FD-SOI transistor is disposed on the first front side. The first back gate is disposed on the first back side. The second device layer includes a second SOI layer, a second FD-SOI transistor and a second back gate. The second SOI layer includes a second front side and a second back side. The second FD-SOI transistor is disposed on the second front side. The second back gate is disposed on the second back side.