3D Ferroelectric FET Memory Arrays for High Density Storage
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Solution Overview
Problem
Conventional memory technologies face challenges in achieving high storage density, low cost-per-bit, and efficient random access capability, particularly in dynamic RAM and storage-class memory, due to limitations in switching speed and retention time.
Innovation Solution
The development of three-dimensional Ferroelectric-gated Field Effect Transistor (FeFET) structures with a semiconductor substrate, channel structures, gate electrode structures, and source/drain electrode structures, where the ferroelectric material is disposed along the channel structures, enabling a capacitor-less, scalable, and compact memory array with logical AND connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DRAM structures are used, then fast switching speed is achieved, but retention time is short and requires frequent refreshing
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional non-ferroelectric materials to ferroelectric materials (such as HfO2-based ferroelectric films), which fundamentally alters the retention mechanism from charge-based to polarization-based, achieving both fast switching and long retention times without frequent refreshing
Solution Approach 2:
The patent employs composite material structures including ferroelectric gate electrodes combined with high-k dielectric materials and metal gate materials, creating a multi-layered gate stack that optimizes both switching performance and data retention characteristics
2Duration of action of stationary object
If conventional floating gate or charge-trap transistor structures are used, then long retention time is achieved, but switching speed is slow and endurance is limited
Solution Approach 1:
The patent changes the fundamental operating mechanism from charge trapping in floating gates to electric field-induced polarization switching in ferroelectric materials, enabling much faster switching speeds (nanosecond range) while maintaining long retention times and improved write/erase endurance
Solution Approach 2:
The patent replaces the mechanical charge injection and trapping mechanism of floating gate transistors with an electric field-based polarization switching mechanism in ferroelectric materials, eliminating the need for high-voltage charge pumping and enabling faster, more reliable operation
3Quantity of substance
If three-dimensional structures are used, then storage density is increased, but fabrication complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertically stacked FeFET structures, where multiple memory layers are stacked along the vertical axis, each layer containing channel structures, gate electrodes, and source/drain regions arranged in perpendicular orientations, thereby increasing storage density without proportionally increasing fabrication complexity
Solution Approach 2:
The patent divides the three-dimensional memory structure into discrete, modular layers including first and second channel structures, first and second gate electrodes, and corresponding source/drain regions, where each layer can be independently formed through sequential fabrication steps, simplifying the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher storage densities, reduced power consumption, and improved switching speed, enabling FeFET-based memory arrays to function as both DRAM and flash memory with enhanced endurance and area efficiency compared to conventional technologies.
Implementation Method 1
an array of gate electrode structures, each having a ferroelectric material
Implementation Method 2
Ferroelectric-gated Field Effect Transistor (FeFET) structures
Data Source
AI summary
Exemplary embodiments of the present disclosure are directed to three-dimensional (3D) Ferroelectric-gated FET (FeFET) structures that can be used to implement circuitry include memory cells, memory arrays, and/or other logic-based circuitry. For example, in exemplary embodiments, 3D FeFET AND memory arrays with vertical and horizontal channel structures are provided.