3D FeFET Structure for MFMIS Capacitance Matching
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Solution Overview
Problem
In designing MFMIS-FETs, reducing the capacitance ratio between the MFM structure and the FET structure is challenging, leading to limitations in device performance due to decreased drain currents and charge trapping issues.
Innovation Solution
Implementing a three-dimensional FET structure with an effective area greater than the footprint, while maintaining the MFM structure's effective area nearly equal to its footprint, to increase the capacitance ratio and reduce write voltages, thereby enhancing endurance and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitance ratio between MFM structure and FET structure is reduced, then device performance is improved, but write voltages increase and charge trapping occurs
Solution Approach 1:
The patent transitions from a planar FET structure to a three-dimensional FET structure with channel regions extending vertically from the substrate. This dimensional change increases the effective area of the FET without proportionally increasing the MFM structure area, thereby reducing the capacitance ratio and improving device performance while managing write voltage requirements
2Reliability
If the effective area of FET is increased to reduce capacitance ratio, then device performance improves, but device complexity increases
Solution Approach 1:
The FET is segmented into multiple channel regions (first, second, third channel regions) that are spatially separated but electrically connected through a common gate electrode. This segmentation increases the effective area and reduces capacitance ratio while maintaining manageable complexity through modular design and shared control elements
3Object-generated harmful factors
If the capacitance ratio is optimized, then charge trapping is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Multiple channel regions are merged under a single common gate electrode, allowing the effective area to be increased through spatial expansion rather than requiring precise control of individual small-area components. This merging approach reduces the capacitance ratio and minimizes charge trapping while avoiding the need for extremely precise manufacturing tolerances on individual features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces charge trapping and write voltages, improving the endurance and performance of MFMIS-FETs by optimizing the capacitance ratio and maintaining a large effective area for the MFM structure.
Implementation Method 1
The metal-ferroelectric-metal structure includes a top electrode and a bottom electrode separated by a ferroelectric layer
Data Source
AI summary
An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.