3D FeFET Memory Array with Stacked Access and Memory Transistors
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Solution Overview
Problem
Traditional two-dimensional (2D) FeFET architectures face limitations in scaling and efficiency, affecting the capacity to meet the increasing demands for higher density in memory arrays, and encounter difficulties in routing interconnects and efficiently utilizing wafer space, leading to higher manufacturing costs and performance degradation of peripheral circuits.
Innovation Solution
A non-volatile memory array with integrated memory and access transistors is developed, featuring a vertically stacked combination of access and memory transistors, including a memory element, to improve memory array density while maintaining or enhancing reliability and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in NAND memory devices increases to achieve higher memory cell density, then memory cell density is improved, but the length of vertical channels increases and memory latency increases
Solution Approach 1:
The patent transitions from traditional two-dimensional planar transistor architectures to three-dimensional vertically stacked transistors. By stacking multiple transistor layers vertically, the invention achieves higher memory cell density without proportionally increasing vertical channel length, thereby improving density while managing latency through optimized vertical stacking rather than simple layer multiplication.
2Ease of manufacture
If traditional 2D FeFET architectures are used, then manufacturing is simpler, but scaling is limited and wafer space utilization is inefficient
Solution Approach 1:
The invention adopts a three-dimensional vertically stacked FeFET architecture where multiple transistor layers are stacked along the vertical direction. This dimensional transition enables significantly higher memory array density by utilizing vertical space rather than only horizontal plane, while maintaining compatibility with existing semiconductor manufacturing processes through standardized vertical stacking techniques.
3Device complexity
If traditional 2D architectures are used, then device structure is simpler, but interconnect routing becomes difficult and wafer space is not efficiently utilized
Solution Approach 1:
The vertically stacked architecture organizes transistors in multiple vertical layers with systematic interconnect routing. Bit lines and gate lines are arranged in alternating patterns across different vertical levels, enabling efficient three-dimensional interconnect routing that reduces wiring complexity and improves space utilization compared to planar two-dimensional layouts.
4Quantity of substance
If vertical channel length increases with more layers, then memory cell density is improved, but peripheral circuit performance degrades
Solution Approach 1:
The patent segments the memory array into multiple distinct vertical layers, each containing transistors with optimized channel lengths. By dividing the overall vertical structure into manageable layers rather than using a single long vertical channel, the invention maintains peripheral circuit performance while achieving high density through systematic layer segmentation and modular stacking.
Data Source
AI summary
A device structure includes base semiconductor rail structures overlying a semiconductor substrate, bottom bit lines contacting a sidewall of a respective one of the base semiconductor rail structures, a two-dimensional array of lower semiconductor pillars, lower gate electrode lines overlying the bottom bit lines and laterally spaced from sidewall segments of a respective column of the lower semiconductor pillars by a lower gate dielectric layer, a two-dimensional array of upper semiconductor pillars, upper gate electrode lines overlying the lower gate electrode lines and laterally spaced from sidewall segments of a respective column of the upper semiconductor pillars by an upper gate dielectric layer, and at least one top bit line contacting top surfaces of a respective row of upper semiconductor pillars.