3D FeFET Memory Stack for Stable Ferroelectric Polarization
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges in maintaining effective memory performance due to issues with ferroelectric material growth and polarization stability, which affects the reliability and readability of digital values stored in memory cells.
Innovation Solution
A 3D memory array is developed using ferroelectric field effect transistors (FeFETs) with vertically stacked memory cells, incorporating a ferroelectric material as gate dielectric and an oxide semiconductor channel region, where ferroelectric portions are discretely disposed on conductive lines and separated by a channel layer, allowing precise control of polarization direction and threshold voltage shifts for improved read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ferroelectric material is used as gate dielectric in vertically stacked memory cells, then memory integration density is improved, but polarization stability deteriorates leading to read errors
Solution Approach 1:
The patent applies local quality by selectively forming inhibitor portions on specific sidewall surfaces of dielectric layers. This creates different surface properties in different locations: the inhibitor portions prevent ferroelectric material formation on certain sidewalls while allowing it on others, enabling precise control over where polarization occurs and improving overall polarization stability in the stacked memory structure.
Solution Approach 2:
The patent changes the physical and chemical parameters of the dielectric layer surfaces by forming self-assembled monolayer inhibitor portions. This modifies surface energy, wettability, and reactivity parameters, which control the nucleation and growth of ferroelectric material during deposition, thereby stabilizing polarization in the high-density stacked configuration.
2Productivity
If feature size is reduced to increase integration density, then more memory cells can be integrated, but ferroelectric material growth control becomes difficult
Solution Approach 1:
The patent segments the continuous sidewall surface into distinct regions by forming discrete inhibitor portions at specific locations. This segmentation allows independent control of ferroelectric material growth on different segments, ensuring uniform and controlled material formation even as overall feature dimensions are reduced to increase integration density.
Solution Approach 2:
The inhibitor portions act as intermediary layers between the dielectric layer and the ferroelectric material. This intermediary controls the interaction at the interface, mediating the growth process to achieve precise control over ferroelectric material thickness and crystallinity despite reduced feature sizes in high-density configurations.
3Stability of the object's composition
If ferroelectric portions are formed on all sidewalls, then device symmetry is maintained, but read window and polarization control are reduced
Solution Approach 1:
The patent deliberately introduces asymmetry by forming inhibitor portions on only select sidewalls rather than all sidewalls. This asymmetric configuration creates distinct polarization regions that enhance the read window and improve polarization control, demonstrating that controlled asymmetry can resolve the contradiction between symmetry and performance in stacked FeFET memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory performance by increasing the orthorhombic phase of ferroelectric materials, improving the read window and reducing errors in digital value storage and retrieval, while maintaining a high integration density and compatibility with back-end-of-line (BEOL) processes.
Implementation Method 1
The plurality of self-assembled monolayers is formed on the sidewall surfaces of the plurality of dielectric layers
Implementation Method 2
performing a surface treatment on the plurality of dielectric layers to modify a surface energy of the plurality of dielectric layers
Implementation Method 3
an annealing process is performed to remove the plurality of self-assembled monolayers
Implementation Method 4
increasing the orthorhombic phase of ferroelectric materials
Data Source
AI summary
Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.