3D FeFET Memory Staircase Structure for High-Density Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given area while maintaining performance and reliability, particularly in the formation of 3D memory devices where high process temperatures and complex layer structures are required.
Innovation Solution
The development of a 3D memory device with a ferroelectric field effect transistor (FeFET) memory circuit featuring vertically stacked memory cells, utilizing a staircase configuration of conductive lines and oxide semiconductor channels, along with a ferroelectric material as a gate dielectric, to enhance integration density and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and reliability deteriorate due to process control difficulties
Solution Approach 1:
The patent transitions from 2D planar memory structures to 3D vertically stacked FeFET memory cells. By stacking multiple memory cells vertically along the channel direction, the integration density increases significantly without requiring further reduction in lateral feature sizes. This dimensional change allows achieving higher density while maintaining manufacturable feature dimensions.
Solution Approach 2:
The patent employs composite material structures including oxide semiconductor channels (e.g., IGZO) combined with ferroelectric gate dielectrics (e.g., HfO2). These composite materials enable simultaneous achievement of low-operating-voltage operation and high-density storage, while maintaining stability during fabrication processes.
2Reliability
If high process temperatures are used to form ferroelectric materials, then better material properties are achieved, but existing components and previously formed layers may be damaged or degraded
Solution Approach 1:
The patent forms the ferroelectric gate dielectric layer and performs necessary thermal processing steps before depositing and patterning the metal electrode layers. This preliminary action allows the ferroelectric material to achieve its optimal crystalline structure and properties through high-temperature processing without subsequent exposure to high temperatures that could damage the metal electrodes or other temperature-sensitive components.
Solution Approach 2:
The fabrication process is segmented into distinct temperature zones and stages: first forming temperature-resistant structures (ferroelectric layer, oxide semiconductor channel), then performing high-temperature annealing to establish material properties, and finally adding temperature-sensitive components (metal electrodes, contact layers) in later low-temperature steps. This segmentation allows each material to be processed at its optimal temperature range.
3Quantity of substance
If vertically stacked memory cells are implemented to increase density, then integration density improves, but device complexity increases due to complex layer structures and fabrication processes
Solution Approach 1:
The patent designs the FeFET memory cell structure where the ferroelectric gate dielectric serves multiple functions: it acts as the gate insulator, provides non-volatile data storage through polarization states, and enables low-operating-voltage operation. The oxide semiconductor channel similarly provides both channel conduction and interface stability. This multi-functionality reduces the need for additional separate layers and components, simplifying the overall structure despite the 3D stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for increased device density and improved performance by enabling higher process temperatures and efficient electrical coupling, facilitating better integration of memory cells and reducing errors in data storage and retrieval.
Implementation Method 1
a ferroelectric material acting as a gate dielectric
Implementation Method 2
an oxide semiconductor (OS) acting as a channel region
Data Source
AI summary
A memory device includes a staircase structure, a plurality of first conductive contacts, a plurality of first drivers and a plurality of second conductive contacts. The staircase structure includes a plurality of first conductive lines and a plurality of first dielectric layers stacked alternately. The first conductive contacts are electrically connected to the plurality of first conductive lines respectively. The second conductive contacts are electrically connected to the plurality of first drivers respectively. The plurality of first conductive contacts and the plurality of second conductive contacts are bonded and disposed between the plurality of first conductive lines and the plurality of first drivers.