3D FeFET NOR Memory Arrays for Endurance and Low Read Latency
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Solution Overview
Problem
Existing ferroelectric memory circuits suffer from low endurance, making them unsuitable for many memory applications.
Innovation Solution
A three-dimensional memory structure is formed with multiple stacks of thin-film ferroelectric field-effect transistors (FeFETs) organized as NOR memory strings, sharing a common source and drain layer, and utilizing a ferroelectric gate dielectric layer made of doped hafnium oxide, with oxide semiconductor channels and simplified fabrication processes to achieve high density and low read-latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If FeFETs are used for ferroelectric memory circuits, then data retention and volatility resistance are improved, but endurance deteriorates due to limited programming cycle tolerance
Solution Approach 1:
The patent transitions from planar 2D memory architecture to 3D vertically stacked memory structures. Multiple FeFET layers are stacked along the vertical direction, enabling high-density memory arrays while maintaining the ferroelectric properties for data retention. The 3D stacking allows independent access to different layers through word lines, achieving both high density and preserved endurance characteristics.
Solution Approach 2:
The patent employs composite material structures including ferroelectric hafnium oxide (HfO2) gate dielectric layers combined with semiconductor channel layers. The ferroelectric layer provides non-volatile data retention, while the semiconductor layer enables transistor switching functionality. This composite structure optimizes both data retention and programming cycle endurance by separating the storage function (ferroelectric layer) from the switching function (semiconductor channel).
2Quantity of substance
If high-density memory arrays are implemented, then storage capacity is improved, but read latency worsens due to increased access time
Solution Approach 1:
The patent implements 3D vertically stacked memory arrays where multiple memory layers are stacked along the vertical axis. This dimensional transition enables exponential growth in storage capacity without proportionally increasing the memory chip footprint. The vertical stacking architecture allows parallel access to multiple layers through independent word line control, maintaining low read latency despite high density.
Solution Approach 2:
The patent divides the high-density memory array into multiple independently addressable layers or blocks. Each layer can be accessed separately through dedicated word lines, enabling parallel read operations. This segmentation allows the memory system to service multiple read requests simultaneously, reducing average read latency while maintaining high total storage capacity.
3Ease of manufacture
If thin-film FeFET structures are used, then manufacturing scalability is improved, but device complexity increases due to multiple layer stacking
Solution Approach 1:
The patent adopts vertical stacking of thin-film FeFET layers to achieve high density while maintaining compatibility with existing planar semiconductor manufacturing processes. The thin-film structure allows sequential deposition of multiple layers using standard thin-film fabrication techniques such as atomic layer deposition (ALD) and chemical vapor deposition (CVD), enabling scalable manufacturing despite increased vertical complexity.
Solution Approach 2:
The patent designs the thin-film FeFET structure with universal components that can be replicated across multiple layers. The same semiconductor channel material, ferroelectric gate dielectric, and electrode structures are reused in each stacked layer, allowing standardized manufacturing processes to be applied repeatedly. This universality reduces process complexity despite the multi-layer architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure achieves high endurance, long data retention, and low voltage operations, enabling high-density, low-cost memory arrays with high-speed, randomly accessed memory circuits.
Implementation Method 1
a ferroelectric gate dielectric layer made of doped hafnium oxide
Data Source
AI summary
A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent a semiconductor channel. In some embodiments, the semiconductor channel is formed by an oxide semiconductor material and the ferroelectric storage transistors are junctionless transistors with no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a first conductive layer as a common source line and a second conductive layer as a common bit line, the first and second conductive layers being in electrical contact with the semiconductor channel. The ferroelectric storage transistors in a multiplicity of NOR memory strings are arranged to form semi-autonomous three-dimensional memory arrays (tiles) with each tile individually addressed and controlled by circuitry in the semiconductor substrate underneath each tile in cooperation with a memory controller.