3D FeRAM Array Layout With CMOS-Under-Area Drivers
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Solution Overview
Problem
Current semiconductor memory technologies, particularly volatile memories like SRAM and DRAM, face challenges in data retention as they lose information when powered off, while non-volatile memories like FeRAM offer fast write/read speeds but require complex fabrication processes that are costly and inefficient.
Innovation Solution
The development of a 3D ferroelectric random access memory (3DFeRAM) using a CMOS under area (CuA) design with a multilayer stack and dual damascene process, which simplifies the fabrication of ferroelectric memory cells by forming a stairstep pattern and using a dual damascene process to create conductive features and dielectric layers, reducing complexity and increasing memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional volatile memory (SRAM/DRAM) is used, then fast access speed is achieved, but data retention capability deteriorates (data loss when powered off)
Solution Approach 1:
The patent transitions from volatile memory materials to ferroelectric materials, changing the physical parameter of data storage from temporary electrical state to stable ferroelectric polarization state, enabling data retention without power
Solution Approach 2:
The patent employs a stacked memory architecture integrating multiple material layers including ferroelectric materials, conductive materials, and dielectric materials to create a composite structure that provides both non-volatile data storage and fast access characteristics
2Reliability
If FeRAM is used to achieve non-volatile storage with fast speed, then data retention and speed are improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent adopts a vertical stacked memory architecture, transitioning from planar 2D layout to 3D vertical stacking, which increases storage density while allowing standard CMOS fabrication processes to be used, thereby reducing fabrication complexity
Solution Approach 2:
The patent divides the memory structure into distinct functional layers (ferroelectric layer, conductive layers, dielectric layers) that can be fabricated using separate, well-established CMOS processes, simplifying the overall manufacturing complexity
3Quantity of substance
If memory cell density is increased, then storage capacity is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent achieves high memory cell density by stacking multiple layers vertically in the Z-dimension, allowing standard 2D CMOS fabrication processes to produce 3D high-density structures without proportionally increasing process complexity
Data Source
AI summary
Semiconductor devices and methods of manufacture are provided wherein a ferroelectric random access memory array is formed with bit line drivers and source line drivers formed below the ferroelectric random access memory array. A through via is formed using the same processes as the processes used to form individual memory cells within the ferroelectric random access memory array.