3D Ferroelectric Capacitor Structure for FRAM Capacitance Tuning
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Solution Overview
Problem
Current Ferroelectric Random Access Memory (FRAM) structures have limited capacitance tuning capability and integration density, which hinders their performance as next-generation non-volatile memory solutions.
Innovation Solution
The integration of a three-dimensional ferroelectric capacitor in FinFET devices, where the capacitance is adjusted by varying the radius and height of the capacitor, allowing for a larger tuning window and increased threshold voltage shift, thereby enhancing memory device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional planar ferroelectric capacitor structure is used, then manufacturing is simpler, but capacitance tuning capability is limited and integration density is low
Solution Approach 1:
The patent transitions from a planar two-dimensional capacitor structure to a three-dimensional structure where the bottom electrode forms a protruding pillar above the substrate. This vertical dimension enables increased capacitance by expanding the electrode surface area in the height direction while maintaining a compact footprint, thereby achieving superior capacitance tuning capability without proportionally increasing device area.
Solution Approach 2:
The patent implements a nested configuration where the ferroelectric layer completely surrounds the bottom electrode pillar, and the top electrode surrounds the ferroelectric layer. This concentric nesting maximizes the effective capacitance-forming interface area within a minimal lateral footprint, enabling high capacitance values while maintaining compact device dimensions for improved integration density.
2Quantity of substance
If capacitor size is increased to improve capacitance, then capacitance value increases, but device footprint increases reducing integration density
Solution Approach 1:
The invention resolves this contradiction by moving the capacitance enhancement from the lateral plane to the vertical dimension. The bottom electrode pillar extends upward from the substrate, and the ferroelectric layer wraps around this vertical structure. This allows the capacitance value to be increased through the height of the pillar and the surface area of the wrapped layers, while the lateral footprint remains compact, achieving high capacitance without proportionally increasing device area.
Solution Approach 2:
The patent enables independent tuning of capacitance by adjusting geometric parameters such as the height and radius of the bottom electrode pillar, the thickness of the ferroelectric layer, and the dimensions of the top electrode. These parameter changes allow precise control of capacitance value without necessarily increasing the lateral footprint, facilitating optimization of both capacitance and integration density.
3Productivity
If three-dimensional ferroelectric capacitor is implemented, then capacitance tuning capability and integration density improve, but manufacturing complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct sequential steps: first forming the bottom electrode pillar structure, then depositing the ferroelectric layer, and finally forming the top electrode. This segmentation of the manufacturing process into manageable stages, where each step builds upon the previous one, makes the complex three-dimensional structure achievable through standard semiconductor fabrication techniques while maintaining production efficiency and integration density.
Data Source
AI summary
A semiconductor device includes a substrate, a fin protruding over the substrate, a gate structure over the fin, a bottom electrode over and electrically coupled to the gate structure, a ferroelectric layer around the bottom electrode, and a top electrode around the ferroelectric layer.