3D Ferroelectric Capacitor for FRAM Integration Density
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Solution Overview
Problem
Current Ferroelectric Random Access Memory (FRAM) structures have limited capacitance tuning capability and integration density, which hinders their performance as next-generation non-volatile memory solutions.
Innovation Solution
The integration of a three-dimensional ferroelectric capacitor within a FinFET device, where the capacitance is adjusted by varying the radius and height of the ferroelectric capacitor, allowing for a larger tuning window and increased threshold voltage shift, thereby enhancing memory device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing FRAM structure is used, then device simplicity is maintained, but capacitance tuning capability is limited
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional capacitor structure by forming the bottom electrode as a conductive column protruding from the substrate and surrounding it with ferroelectric and top electrode layers. This vertical stacking in the third dimension enables significantly larger capacitance values without increasing the lateral footprint, thereby achieving high capacitance tuning capability while maintaining compact device geometry.
Solution Approach 2:
The patent implements a nested structure where the ferroelectric layer is formed around the bottom electrode column, and the top electrode layer is formed around the ferroelectric layer. This concentric nesting arrangement maximizes the effective capacitance area within a minimal lateral space, allowing for large capacitance values in a compact footprint and enabling versatile capacitance tuning without proportionally increasing device area.
2Reliability
If capacitance is increased to improve memory performance, then threshold voltage shift increases, but device footprint increases
Solution Approach 1:
The patent achieves large capacitance values required for high reliability and large threshold voltage shift by extending the capacitor structure vertically into the third dimension. The bottom electrode forms a conductive column that protrudes from the substrate, and the ferroelectric and top electrode layers wrap around this column, creating a tall, narrow capacitor structure. This vertical expansion provides large capacitance without increasing the lateral device footprint.
Solution Approach 2:
The patent enables continuous tuning of the capacitor radius and height parameters to optimize the capacitance value for specific application requirements. By independently controlling the radius of the bottom electrode column and the height of the protruding structure, the design can achieve the precise capacitance value needed for desired threshold voltage shift while maintaining minimal footprint, thus optimizing reliability without excessive area consumption.
3Productivity
If integration density is increased to improve manufacturing efficiency, then capacitance tuning capability deteriorates
Solution Approach 1:
The three-dimensional capacitor structure concentrates the capacitance-generating volume vertically rather than laterally. This allows multiple capacitors to be packed more densely in the lateral plane since each capacitor occupies minimal footprint area. The high capacitance value is achieved through the vertical height of the structure rather than its lateral dimensions, enabling both high integration density and adequate capacitance tuning capability to coexist.
Solution Approach 2:
The nested concentric structure of bottom electrode column, ferroelectric layer, and top electrode layer creates a compact capacitor unit with minimal lateral footprint. This efficient space utilization allows more capacitors to be integrated per unit area, achieving high integration density. Simultaneously, the vertical stacking provides sufficient capacitance volume for adequate tuning capability, resolving the trade-off between density and versatility.
Data Source
AI summary
A semiconductor device includes a substrate, a fin protruding over the substrate, a gate structure over the fin, a bottom electrode over and electrically coupled to the gate structure, a ferroelectric layer around the bottom electrode, and a top electrode around the ferroelectric layer.