3D Ferroelectric Flash Memory With Back Gate Reliability Control
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Solution Overview
Problem
Three-dimensional flash memory arrays experience degradation in cell characteristics and reliability due to increased integration, particularly with vertical memory cells.
Innovation Solution
Incorporation of a ferroelectric layer between word lines and a channel layer with a back gate structure inside the channel layer for data storage, utilizing the ferroelectric layer to change and maintain charge states, and employing back gates for voltage application during program, erase, and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cells are vertically stacked to increase degree of integration, then storage capacity increases, but cell characteristics and reliability degrade
Solution Approach 1:
The patent transitions from purely vertical stacking to a hybrid architecture that incorporates horizontal scaling through the introduction of back gates extending in the first direction (horizontal) while channel layers extend in the second direction (vertical). This dimensional change allows integration capacity to increase without the detrimental effects of excessive vertical stacking, thereby maintaining cell characteristics and reliability.
Solution Approach 2:
The patent divides the memory structure into multiple strings, each with its own back gate, allowing independent control and optimization of each string's characteristics. This segmentation enables better management of cell characteristics while achieving high integration through the combined vertical-channel and horizontal-backgate architecture.
2Quantity of substance
If vertical memory cells are used to increase integration, then storage density increases, but reliability degrades
Solution Approach 1:
The patent applies different structural qualities to different regions: vertical channel layers provide high storage density in the vertical dimension, while horizontal back gates provide reliable voltage control in the horizontal dimension. This local differentiation of structural qualities allows the system to achieve both high storage density and high reliability simultaneously.
Solution Approach 2:
The patent creates a composite structure combining vertical channel layers (for density) with horizontal back gates (for reliability). This composite architecture leverages the strengths of both vertical and horizontal configurations, achieving high storage density through vertical stacking while maintaining reliability through horizontal back gate control.
3Reliability
If back gate structure with ferroelectric layer is implemented, then cell characteristics improve, but device complexity increases
Solution Approach 1:
The back gate structure serves multiple functions simultaneously: it provides voltage control for the channel layer, enables ferroelectric data storage, and allows independent string control. This multi-functionality justifies the increased structural complexity by delivering significant improvements in cell characteristics and reliability.
Solution Approach 2:
The patent implements a nested structure where the back gate is positioned within or adjacent to the vertical channel layer, with the ferroelectric layer integrated between the back gate and word lines. This nested arrangement optimizes space utilization and allows the complex multi-component structure to achieve high integration without excessive footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves cell characteristics and reliability while enabling improved horizontal scaling by using the ferroelectric layer as data storage and optimizing memory operations through back gate voltage control.
Implementation Method 1
utilizing the ferroelectric layer to change and maintain charge states
Implementation Method 2
employing back gates for voltage application during program, erase, and read operations
Data Source
AI summary
Disclosed is a three-dimensional flash memory using a ferroelectric layer on the basis of a back gate structure. According to an embodiment, a three-dimensional flash memory comprises: a plurality of word liens extending on a substrate in a horizontal direction and sequentially stacked; and a plurality of strings extending through the plurality of word lines on the substrate in one direction, each of the plurality of strings including a channel layer extending in the one direction and a ferroelectric layer extending in the one direction to surround the channel layer, wherein a back gate extending in the one direction and an insulating layer extending in the one direction to surround the back gate are disposed inside the channel layer, and the channel layer and the ferroelectric layer constitute a plurality of memory cells corresponding to the plurality of word lines, wherein the ferroelectric layer is formed of a ferroelectric material and used as data storage by changing and maintaining the states of electric charges.