3D Ferroelectric Memory Array Layout for High-Density TFT Storage
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Solution Overview
Problem
Existing semiconductor memories, such as volatile RAM and non-volatile FeRAM, face challenges in achieving high device density and efficient data storage with fast read/write speeds, particularly in three-dimensional configurations.
Innovation Solution
A three-dimensional memory array is developed using programmable thin film transistors (TFTs) with source lines and bit lines, featuring extension regions as back gates, and data storage layers between word lines, utilizing ferroelectric materials for polarization-based data storage, and a multiple-patterning process to enhance structural stability and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory structures are implemented to increase device density, then storage capacity improves, but manufacturing complexity and structural stability deteriorate
Solution Approach 1:
The patent applies segmentation by dividing the memory structure into discrete stacked layers (first memory layer, second memory layer, third memory layer) with alternating conductive and insulating materials. This segmentation enables systematic fabrication through repeated deposition cycles while maintaining structural integrity and simplifying the manufacturing process for three-dimensional architectures.
Solution Approach 2:
The patent implements nesting by creating a hierarchical structure where conductive layers are embedded within insulating layers, which are in turn embedded within a matrix material. This nested arrangement allows multiple functional layers to be integrated vertically, increasing device density while maintaining a compact three-dimensional structure that is manufacturable through sequential processing steps.
2Speed
If ferroelectric materials are used for data storage, then write/read speed improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the thickness of conductive and insulating layers to optimize ferroelectric performance. By controlling layer thickness parameters within specific ranges, the patent achieves the desired write/read speeds while maintaining manufacturability through standard deposition processes, balancing performance requirements with manufacturing precision capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves memory array performance by controlling surface potential during write operations, enhancing device density, and reducing errors in read operations, while maintaining fast write/read speeds.
Implementation Method 1
utilizing ferroelectric materials for polarization-based data storage
Data Source
AI summary
In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.