3D Ferroelectric Memory With Backside Gate Electrode
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Solution Overview
Problem
Current three-dimensional ferroelectric memory devices face challenges in efficiently integrating a backside gate electrode to enhance memory storage capabilities and manufacturing processes, particularly in forming complex structures with ferroelectric material layers and semiconductor channels.
Innovation Solution
The development of a three-dimensional memory device structure comprising alternating stacks of insulating and conductive strips over a substrate, with line trenches filled with memory stack structures that include a ferroelectric material layer, front-side and backside gate dielectrics, and a backside gate electrode, allowing for vertical semiconductor channels and precise layer formation through sequential deposition and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a backside gate electrode is integrated into three-dimensional ferroelectric memory devices, then memory storage capabilities and operational efficiency are enhanced, but device structure complexity increases
Solution Approach 1:
The device is divided into distinct functional segments: front-side gate structures, backside gate electrode, ferroelectric material layers, and semiconductor channels. Each segment is formed through separate deposition and etching processes, allowing independent optimization and simplifying the overall integration of the complex structure.
Solution Approach 2:
The patent transitions from two-dimensional planar structures to three-dimensional vertical structures by stacking multiple layers (ferroelectric material, gate dielectrics, conductive strips, insulating strips) and forming vertical semiconductor channels. This dimensional change increases storage density while the backside gate electrode provides additional control dimension for memory operations.
2Quantity of substance
If complex structures with ferroelectric material layers and semiconductor channels are formed, then memory storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
Alternating stacks of insulating layers and spacer material layers are formed beforehand to serve as precise templates and spacers. These pre-formed structures define the positions and dimensions of subsequent ferroelectric material layers and semiconductor channels, ensuring high manufacturing precision through self-aligned processes.
Solution Approach 2:
Gate dielectric layers and spacer material layers act as intermediary structures between the substrate and the final memory active structures. These intermediaries provide precise spacing, electrical isolation, and structural support, enabling accurate formation of thin ferroelectric layers and vertical channels without direct contact between conflicting structural elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables improved memory storage density and operational efficiency by effectively utilizing ferroelectric material properties and semiconductor channel interactions, enhancing data encoding and retrieval in a nonvolatile manner.
Implementation Method 1
Ferroelectric memory device refers to a memory device in which information is stored in the ferroelectric state of a ferroelectric material. The ferroelectric state can affect the conductance of an adjacent material portion through the effect of the electrical charges that accumulate at an interface with the adjacent material portion.
Data Source
AI summary
A ferroelectric memory device includes an alternating stack of insulator layers and electrically conductive layers and located over a top surface of a substrate, a memory stack structure vertically extending through the alternating stack and including a ferroelectric material layer, a front-side gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front-side gate dielectric, a backside gate dielectric contacting the vertical semiconductor channel, and a backside gate electrode contacting the backside gate dielectric. Portions of the ferroelectric material layer adjacent to the electrically material layers can be programmed with polarization states to store data.