3D Ferroelectric Memory Stack With Buffer Layers for Polarization Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges in maintaining reliable memory storage and retrieval due to the need for precise control of ferroelectric materials in memory cells, particularly in ferroelectric memory devices like FeFETs, where polarization direction changes are critical for data storage.
Innovation Solution
A ferroelectric memory device is designed with a 3D memory array structure using vertically stacked FeFET memory cells, incorporating a ferroelectric material as a gate dielectric, an oxide semiconductor channel region, and a buffer layer to enhance uniform growth and performance, allowing for precise voltage control to switch polarization directions and improve data storage reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but control of ferroelectric materials becomes less reliable
Solution Approach 1:
The patent applies local quality by introducing a buffer layer with specific material properties (different from both the ferroelectric layer and the underlying layer) at the interface region where stress and polarization control are critical. This localized modification of material composition at the interface improves the reliability of ferroelectric material control without requiring changes to the overall device dimensions, thereby maintaining high integration density while enhancing local material control.
Solution Approach 2:
The patent employs composite materials by creating a multi-layer structure consisting of the ferroelectric material layer, the buffer layer, and the underlying layer. This composite structure allows each layer to contribute its specific properties: the ferroelectric layer provides polarization switching, the buffer layer provides stress management and interface quality, and the underlying layer provides structural support. This composite approach enables reliable ferroelectric control at scaled dimensions.
2Volume of moving object
If ferroelectric material layer is made thinner to reduce feature size, then integration density increases, but polarization control precision deteriorates
Solution Approach 1:
The buffer layer acts as an intermediary between the thin ferroelectric layer and the underlying layer. It mediates the stress and interface effects that would otherwise directly impact the polarization control of the ultra-thin ferroelectric layer. This intermediary structure enables precise polarization control even when the ferroelectric layer is made extremely thin, as the buffer layer compensates for interface imperfections and stress variations.
Solution Approach 2:
The patent utilizes parameter changes by carefully controlling the thickness, composition, and material properties of the buffer layer to optimize its stress and interface characteristics. By adjusting these parameters, the buffer layer can be tailored to provide the exact level of stress management and interface quality needed to maintain polarization control precision in ultra-thin ferroelectric layers.
3Reliability
If buffer layer is added to improve uniform growth, then manufacturing complexity increases, but data storage reliability improves
Solution Approach 1:
The buffer layer is designed with specific parameter ranges (thickness, composition, material type) that can be controlled using existing manufacturing processes. By optimizing these parameters, the buffer layer provides significant improvements in uniform growth and interface quality while remaining compatible with standard semiconductor manufacturing techniques, thereby limiting the increase in manufacturing complexity.
Solution Approach 2:
The buffer layer is formed using composite material approaches that leverage existing material systems and deposition techniques. This allows the buffer layer to be integrated into the manufacturing process without requiring entirely new process equipment or methods, thus improving data storage reliability while minimizing the increase in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D array structure with a ferroelectric material and buffer layer enables efficient and error-prone data storage and retrieval by providing a larger threshold voltage shift, enhancing the reliability of digital data storage in ferroelectric memory devices.
Implementation Method 1
A ferroelectric layer is formed on the sidewall of the trench, wherein the ferroelectric layer covers sidewalls of the buffer layers and sidewalls of the conductive layers
Implementation Method 2
one buffer layer is disposed between the ferroelectric layer and each of the plurality of dielectric layers
Data Source
AI summary
A device includes a multi-layer stack, a channel layer, a ferroelectric layer and buffer layers. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The ferroelectric layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The buffer layers include a metal oxide, and one of the buffer layers is disposed between the ferroelectric layer and each of the plurality of dielectric layers.