3D Ferroelectric Memory Stacked Layers Domain Wall Conduction
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Solution Overview
Problem
Conventional ferroelectric memory devices face challenges in storage density, capacity, cost, and power consumption, particularly in the Post-Moore era, where increased crosstalk and higher costs per word and bit become bottlenecks, necessitating innovative solutions for semiconductor memory chips.
Innovation Solution
A three-dimensional non-volatile ferroelectric memory is developed, featuring a ferroelectric memory array structure with multiple layers of ferroelectric memory cells stacked orthogonally, where word lines and bit lines are connected through a domain wall conductive passage established between ferroelectric memory cells and reference ferroelectric bodies, allowing for unidirectional conduction and efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional ferroelectric memory structure is used, then device fabrication is simpler, but storage density and capacity are limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar memory structure to a three-dimensional stacked structure with multiple ferroelectric layers arranged vertically. This dimensional change enables significantly higher storage density by utilizing the vertical space, with multiple memory layers stacked along the thickness direction of the substrate, thereby increasing the quantity of storage units per unit area.
Solution Approach 2:
The memory device is divided into multiple independent ferroelectric layers, each functioning as a separate memory stack. Each layer contains complete memory cells with word lines, bit lines, and ferroelectric capacitors, allowing independent operation and selection of specific layers through voltage control, thus achieving high storage density while maintaining manageable structural complexity.
2Quantity of substance
If more memory cells are integrated to increase capacity, then crosstalk between cells increases
Solution Approach 1:
By stacking memory layers in the vertical direction, the patent increases storage capacity without increasing lateral cell density. This spatial separation in the vertical dimension reduces electromagnetic coupling and crosstalk between adjacent cells, as each layer is physically separated from others by insulating barriers and spacing.
Solution Approach 2:
The patent introduces reference ferroelectric bodies and insulating barrier layers as intermediary structures between adjacent memory cells and layers. These intermediaries act as electrical isolators that prevent signal interference and crosstalk while maintaining the compact stacked architecture, enabling high-capacity storage without compromising signal integrity.
3Reliability
If conventional readout mechanism is used, then read current is large consuming more power
Solution Approach 1:
The patent replaces the conventional voltage-based readout mechanism with a current-based domain wall conduction detection mechanism. Instead of measuring voltage changes across the ferroelectric capacitor, the system detects the presence and movement of domain walls through conductive pathways, enabling lower power consumption while maintaining reliable data readout capability.
Solution Approach 2:
The domain wall conduction mechanism utilizes the intrinsic ferroelectric properties and spontaneous polarization of the material to generate detectable electrical signals during readout. The ferroelectric domains themselves serve as the conduction pathways, eliminating the need for external high-power readout circuits and reducing overall power consumption while preserving data integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances storage density, reduces crosstalk, and lowers power consumption, enabling simpler Crossbar structures and lower manufacturing costs per unit storage capacity, while maintaining good data retention performance.
Implementation Method 1
Conventional ferroelectric random access memory (FRAM) is a non-volatile memory which stores data by using two different polarization orientations of a ferroelectric domain (or referred to as 'electric domain') in an electric field as logic information ('0' or '1')
Implementation Method 2
a domain wall conductive passage can be established between the ferroelectric memory cell and the reference ferroelectric body adjacent thereto, wherein the word line and bit line on the two sides of the ferroelectric memory cell can be electrically connected by the domain wall conductive passage
Data Source
AI summary
Disclosed is a three-dimensional non-volatile ferroelectric memory including a ferroelectric memory array structure, wherein the ferroelectric memory array structure includes multiple layers of ferroelectric memory cell array disposed in a stacked way, and each layer of the ferroelectric memory cell array includes ferroelectric memory cells arranged in rows and columns; wherein word lines and bit lines which are substantially orthogonal to each other are oppositely disposed on two sides of the corresponding ferroelectric memory cell respectively, and a reference ferroelectric body is disposed adjacent to the corresponding ferroelectric memory cell. A polarization direction of an electric domain in the ferroelectric memory cell is not perpendicular to an electric field direction of a write voltage signal applied to the word line and the bit line; and when the write voltage signal is applied between the word line and the bit line.