3D Ferroelectric Memory Stacking for DRAM Density Limits
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Solution Overview
Problem
Current DRAM technology faces limitations in storage density, power consumption, and scalability, as it is nearing the end of its lateral scaling roadmap and cannot be easily stacked into 3D architectures, requiring a more efficient and denser memory solution.
Innovation Solution
The development of three-dimensional ferroelectric memory structures using ferroelectric memory cells with a ferroelectric layer, such as hafnium oxide, which enables non-volatile storage and rapid switching speeds, allowing for the creation of dense, low-latency memory structures like FeFETs and FTJs in various architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM technology is used, then fast data transfer performance is achieved, but storage density is limited and power consumption is relatively high
Solution Approach 1:
The patent transitions from two-dimensional lateral scaling to three-dimensional vertical stacking by arranging memory cells in a 3D configuration with bit lines extending in first directions and word lines in second directions perpendicular to the bit lines. This dimensional change enables significantly higher storage density while maintaining fast access speeds and reducing power consumption per bit.
2Quantity of substance
If lateral scaling of DRAM is continued, then storage capacity increases, but scalability is reached and further improvement becomes difficult
Solution Approach 1:
The invention employs three-dimensional stacking architecture where memory cells are arranged vertically with multiple layers of bit lines and word lines intersecting at right angles. This 3D configuration provides a scalable path for increasing storage capacity beyond the limitations of lateral scaling, allowing continuous adaptation and expansion.
3Quantity of substance
If DRAM is stacked into 3D architectures, then storage density improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory structure into repeating modular units consisting of alternating layers of first and second conductive materials, with bit lines and word lines formed as separate interleaved stacks. This segmentation into standardized modules simplifies the manufacturing process by enabling repetitive fabrication steps and reducing overall device complexity despite the 3D architecture.
Solution Approach 2:
The invention utilizes alternating layers of conductive materials with different properties (first conductive material layers for bit lines, second conductive material layers for word lines) to simplify the formation process. By changing material parameters and leveraging the distinct electrical properties of different conductive layers, the patent reduces manufacturing complexity while achieving high storage density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a high-density, low-power, and fast memory solution that surpasses conventional DRAM performance, enabling scalable and efficient non-volatile storage with reduced power consumption and increased storage capacity.
Implementation Method 1
each ferroelectric memory cell comprising a ferroelectric layer adapted to provide non-volatile storage of data
Implementation Method 2
a tunnel barrier layer contactingly engaging the ferroelectric layer, and opposing first and second conductive layers between which the ferroelectric layer and the tunnel barrier are disposed
Data Source
AI summary
A memory device has ferroelectric memory cells arranged into a three-dimensional (3D) structure. Each ferroelectric memory cell has a ferroelectric layer adapted to provide non-volatile storage of data. In some cases, each ferroelectric memory cell is arranged as a ferroelectric field effect transistor (FeFET) comprising a source region, a drain region, and a control gate region, the control gate region comprising the ferroelectric layer. In other cases, each ferroelectric memory cell is arranged as a ferroelectric tunnel junction (FTJ) comprising opposing conductive electrode layers between which the ferroelectric layer and a tunnel junction layer are contactingly disposed. The ferroelectric layer may be formed of HfO2, ZrO2, Hf1-xZxO2, etc. The tunnel barrier layer may be formed of Al2O3, MgO, SrTiO3, etc. The memory can be used as a substitute for DRAM, a main memory in a data storage device, a data cache, etc.