3D Ferroelectric TFT Memory Array With Conductive Interface Layer

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Solution Overview

Problem

Current semiconductor memory technologies face challenges in achieving high density and efficient data storage with low error rates, particularly in volatile and non-volatile memory applications, due to limitations in write and read operations and retention times.

Innovation Solution

A 3D memory array is developed with vertically stacked memory cells, each comprising a thin film transistor (TFT) with a ferroelectric memory film, an oxide semiconductor channel region, and conductive features between the memory film and the channel region, which improves data retention and reduces defects at the interface, enhancing charge screening and operational efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional memory structures are used, then manufacturing processes are simpler, but device density is lower

Engineering Contradiction:
Improvedevice densityVSAvoidmemory structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D memory cell arrangements to a 3D vertical stacking architecture. Multiple memory cells are stacked along the vertical dimension, with bit lines extending through multiple cell layers. This dimensional change enables significantly higher device density without proportionally increasing manufacturing complexity, as the basic cell structure remains similar but is arranged in three dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If interface quality between memory film and channel region is poor, then manufacturing is easier, but error rates in read/write operations increase

Engineering Contradiction:
Improveerror rate in read/write operationsVSAvoidinterface quality between memory film and channel region
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces a conductive feature layer positioned between the ferroelectric memory film and the oxide semiconductor channel region. This intermediary conductive layer serves multiple functions: it improves the electrical interface between the memory film and channel, reduces defects at the junction, and enhances charge screening. The conductive feature acts as a mediator that resolves the interface quality issue without requiring extremely precise manufacturing of direct contact between the memory film and channel region.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If data retention time is insufficient, then memory operation is faster, but data storage reliability decreases

Engineering Contradiction:
Improvedata retention timeVSAvoiddata retention time
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent employs a composite material structure consisting of a ferroelectric memory film combined with an oxide semiconductor channel region and a conductive feature layer. The ferroelectric material provides non-volatile data retention through its polarized state, while the oxide semiconductor provides stable electrical characteristics. This composite structure achieves both fast operation and long data retention times, resolving the contradiction between speed and retention reliability.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The 3D memory array increases device density, improves data retention times, and reduces errors in read/write operations by utilizing ferroelectric materials and conductive features to enhance the quality of the memory film interface, leading to more reliable and efficient data storage.

Implementation Method 1

Each memory cell includes a ferroelectric memory film, an oxide semiconductor channel region

Methodology Applied
Scientific EffectFerroelectricity:

Implementation Method 2

conductive features between the memory film and the channel region, which improves data retention and reduces defects at the interface, enhancing charge screening and operational efficiency

Methodology Applied
Scientific EffectCharge screening:

Data Source

PatentUS12167606B2Memory device and method of forming thereof
Publication Date: 2024.12.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12167606B2 patent drawing
  • US12167606B2 patent drawing
  • US12167606B2 patent drawing

AI summary

A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line, an oxide semiconductor (OS) layer contacting a source line and a bit line, and a conductive feature interposed between the memory film and the OS layer. The memory film is disposed between the OS layer and the word line. A dielectric material covers sidewalls of the source line, the memory film, and the OS layer.