3D Ferroelectric Memory Cells With Shortened Segments for Lower Capacitance

The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked along the vertical direction, with gate electrodes, channel layers, and ferroelectric layers arranged in multiple tiers. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate rather than only the planar area.

The ferroelectric layer is segmented into discrete ferroelectric segments that do not extend continuously along the entire channel length. Each ferroelectric segment is positioned only in specific regions where needed for memory cell operation, typically beneath the gate electrode and channel layer intersections. This segmentation reduces the overlapping area between word lines and bit lines, thereby reducing parasitic capacitance while still providing sufficient ferroelectric effect for memory functionality.

The patent employs preliminary patterning actions to define alignment structures and sacrificial layers before forming the stacked memory cells. Word lines, bit lines, and source lines are pre-formed with precise patterns that serve as templates for subsequent layer deposition. Sacrificial layers are deposited and patterned in advance to guide the formation of channel layers and ferroelectric layers, ensuring accurate vertical alignment without requiring extremely tight tolerances in later processing steps.