3D Ferroelectric Memory Structure for Faster Low-Voltage Programming
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Solution Overview
Problem
Current 3D NAND flash memory devices face challenges in achieving high programming rates and low operating voltages, which are essential for compact and reliable solid-state drives, particularly in integrating ferroelectric field-effect transistors (FeFETs) effectively.
Innovation Solution
A 3D ferroelectric memory device design featuring a substrate with stacked insulating layers, gate electrodes, gate insulating layers, a ferroelectric layer, intermediate electrodes, and a channel layer, where the intermediate electrodes are configured with a specific polarity, and the ferroelectric layer is in contact with the insulating layers, enhancing the memory window and on-current through a three-dimensional channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 3D NAND flash memory structure is used, then device integration is achieved, but programming rate is slow and operating voltage is high
Solution Approach 1:
The patent transitions from planar 2D channel structure to a 3D vertical channel structure that extends through multiple stacked insulating layers. The channel layer forms a vertical pathway perpendicular to the substrate, with gate electrodes wrapping around the channel from multiple directions (bottom gate and side gates), creating a three-dimensional field-effect transistor architecture that enables faster programming while maintaining compact integration.
Solution Approach 2:
The patent implements a nested structure where multiple gate electrodes are positioned at different vertical levels around the channel layer. The bottom gate electrode is positioned first, followed by intermediate electrodes between insulating layers, and side gate electrodes wrapping around the channel. This nested arrangement allows multiple gating functions to be integrated within a compact vertical space, enhancing control over the channel and improving programming speed.
2Use of energy by moving object
If conventional 3D NAND flash memory structure is used, then device integration is achieved, but operating voltage remains high
Solution Approach 1:
The patent applies different gate electrode configurations at different locations along the channel. The bottom gate electrode provides primary control, while side gate electrodes positioned at specific vertical levels provide localized control over specific channel regions. This localized gating allows for optimized voltage distribution, reducing the overall operating voltage required while maintaining reliable memory performance through distributed control.
Solution Approach 2:
The patent employs a composite structure combining multiple insulating layers with different properties (first insulating layer, second insulating layer, third insulating layer) and multiple gate electrode materials. The ferroelectric layer is integrated between the channel and intermediate gates, providing non-volatile memory functionality. This composite architecture enables low operating voltage operation while maintaining high reliability through the synergistic combination of different functional materials and structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design increases the memory window and on-current of the FeFETs by applying charges to the intermediate electrodes, improving the programming rate and reducing operating voltage, thereby addressing the limitations of existing 3D NAND flash memory devices.
Implementation Method 1
a ferroelectric layer in contact with side surfaces of the plurality of insulating layers
Implementation Method 2
Each of the plurality of intermediate electrodes may be configured to include a charge of a first polarity
Data Source
AI summary
Provided is a three-dimensional (3D) ferroelectric memory device. The 3D ferroelectric memory device includes a substrate, a plurality of insulating layers stacked on the substrate, a plurality of gate electrodes between the plurality of insulating layers, a plurality of gate insulating layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of gate insulating layers, a ferroelectric layer in contact with the plurality of intermediate electrodes and the plurality of insulating layers, and a channel layer in contact with the ferroelectric layer.