3D Ferroelectric Memory Vertical Stacking Density
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Solution Overview
Problem
As semiconductor memory technologies shrink, they face design and process challenges in reducing cost per bit while maintaining data retention and efficiency, particularly in non-volatile memory devices like ferroelectric memory, where scaling leads to increased complexity and reduced performance.
Innovation Solution
The development of a monolithic three-dimensional memory array using ferroelectric field-effect transistors (Fe-FETs) with a gate oxide made of doped orthorhombic phase hafnium oxide, allowing for vertical stacking of memory cells above a substrate, enabling efficient data storage and retrieval through controlled voltage and polarization states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional memory arrays are used, then manufacturing processes are simpler, but storage density and chip area efficiency are limited
Solution Approach 1:
The patent transitions from conventional two-dimensional memory arrays to a three-dimensional monolithic stacked architecture. Multiple memory layers are vertically stacked above a single substrate without intervening substrates, enabling significantly higher storage density by utilizing the third dimension (vertical stacking) while maintaining compatibility with existing manufacturing processes
2Quantity of substance
If process geometries are shrunk to reduce cost per bit, then storage capacity increases, but design and process challenges increase and performance decreases
Solution Approach 1:
Instead of continuing to shrink lateral dimensions which exacerbates manufacturing challenges and performance degradation, the patent stacks multiple memory layers vertically. This approach increases storage capacity by utilizing the vertical dimension while maintaining larger, more manufacturable lateral geometries, thereby avoiding the worsening manufacturing precision issues associated with extreme scaling
Solution Approach 2:
The patent employs a composite structure consisting of multiple memory layers, each containing ferroelectric materials (such as hafnium oxide) integrated with transistor structures. This composite architecture enables simultaneous achievement of high storage capacity and maintained manufacturing feasibility through proven material systems and processes
3Quantity of substance
If more memory layers are stacked, then storage density increases, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent implements monolithic three-dimensional stacking where multiple memory layers are formed vertically above a single substrate without requiring intermediate substrates or complex assembly steps. This approach increases storage density while maintaining manufacturing ease by using a unified monolithic process rather than multi-step assembly of separate layers
Solution Approach 2:
The patent designs a universal memory cell structure that can be replicated across multiple layers using the same fabrication processes. The monolithic stacked architecture uses consistent materials and processes for each layer, enabling scalable production where the same manufacturing toolkit can produce arbitrary numbers of stacked layers without requiring new process development for each additional layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances data storage density and efficiency by allowing multiple layers of memory cells to be stacked without intervening substrates, reducing chip area and improving programming speeds, while maintaining data retention and reducing operational complexities.
Implementation Method 1
a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line
Data Source
AI summary
A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.