3D Ferroelectric Memory Vertical Stacking Density
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Solution Overview
Problem
Existing ferroelectric memory devices face limitations in memory cell density, making it challenging to achieve high performance and cost-effectiveness due to the limitations of planar process and fabrication techniques as feature sizes approach lower limits.
Innovation Solution
The development of three-dimensional (3D) ferroelectric memory devices with vertically stacked ferroelectric memory cells, including capacitors and transistors, using a ferroelectric layer composed of oxygen and specific metals, and electrode materials like silicon and transparent conductive oxides, to enhance memory density and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar process and fabrication techniques are used, then manufacturing simplicity is maintained, but memory cell density is limited
Solution Approach 1:
The patent transitions from planar (2D) memory cell layout to three-dimensional (3D) vertically stacked architecture. Multiple memory cells are stacked along the vertical direction, with capacitors and transistors arranged in layers, enabling significantly higher memory cell density per unit area while managing fabrication complexity through systematic process design
2Quantity of substance
If feature sizes are reduced to increase density, then memory cell density improves, but manufacturing precision requirements increase
Solution Approach 1:
Instead of continuously reducing lateral feature sizes which demands ever-increasing manufacturing precision, the patent stacks memory cells vertically. This approach increases density by utilizing the third dimension (vertical stacking of capacitors and transistors), thereby avoiding the need to push lateral feature sizes to extremely small dimensions that would require prohibitively high precision manufacturing
3Quantity of substance
If vertically stacked memory cells are implemented, then memory density increases, but device complexity increases
Solution Approach 1:
The vertically stacked memory cell is divided into distinct functional segments: capacitor portions (including first and second electrodes with ferroelectric layers) and transistor portions (including channels and gates), arranged in alternating layers. This segmentation allows each component to be independently designed, fabricated, and controlled, managing the overall device complexity through modular architecture
Solution Approach 2:
The patent employs shared structures among multiple stacked memory cells, such as common bit lines, word lines, and substrate connections that serve multiple cells simultaneously. This multi-functionality reduces the number of independent components needed, thereby managing device complexity while maintaining high density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D architecture increases memory density, improves performance, and reduces the cost-per-byte for storage by overcoming the limitations of planar ferroelectric memory devices, enabling more efficient use of space and resources.
Implementation Method 1
A ferroelectric material has a nonlinear relationship between the applied electric field and the apparent stored charge and thus, can switch polarity in an electric field
Data Source
AI summary
Embodiments of three-dimensional (3D) ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a 3D ferroelectric memory device includes a substrate and a plurality of ferroelectric memory cells each extending vertically above the substrate. Each of the ferroelectric memory cells includes a capacitor and a transistor electrically connected to the capacitor. The capacitor includes a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode. The transistor includes a channel structure, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor.