3D Ferroelectric NOR Memory Strings With Channel-All-Around Access
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Solution Overview
Problem
Current memory technologies face challenges in achieving high-density, scalable, and efficiently addressable memory structures that can support advanced computing systems with high capacity and low latency, particularly in using ferroelectric materials effectively in three-dimensional NOR memory strings.
Innovation Solution
The development of a three-dimensional memory structure utilizing channel-all-around ferroelectric memory transistors with a multilayer film stack and local word line structures, where each memory stack includes concentric layers of an oxide semiconductor, ferroelectric dielectric, and gate conductor, enabling individual access and high-density memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar memory structures are used, then manufacturing is simpler, but memory density and capacity are limited
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertical memory stacks, enabling higher memory density by utilizing the vertical dimension. Multiple active layers are stacked above a common substrate, with each layer containing memory cells that can be independently addressed through word lines extending in different orientations.
Solution Approach 2:
The patent implements nested structures where multiple active layers are vertically stacked, each containing concentric or nested word line structures. The channel-all-around transistor architecture nests the channel region within the gate electrode structure, maximizing space utilization and enabling higher density without proportionally increasing footprint area.
2Quantity of substance
If three-dimensional memory stacks are implemented, then memory capacity increases, but read latency and access efficiency may worsen
Solution Approach 1:
The patent divides the three-dimensional memory stack into multiple independently addressable active layers, each with its own set of word lines. This segmentation allows parallel access to different layers, reducing the time penalty associated with deep three-dimensional structures by enabling simultaneous read operations across multiple segments.
Solution Approach 2:
The patent implements dynamic addressing schemes where word lines can be selectively activated in different layers and orientations. The channel-all-around transistor design allows for dynamic control of current flow paths, enabling flexible access patterns that can optimize read latency by selecting the most efficient path to the required data location.
3Reliability
If channel-all-around ferroelectric transistors are used, then memory performance and retention improve, but fabrication complexity increases
Solution Approach 1:
The patent utilizes ferroelectric materials with specific phase transitions and polarization characteristics to achieve non-volatile memory retention. By controlling the crystalline phase and polarization state of the ferroelectric layer through precise deposition parameters and thermal processing, the patent achieves reliable data retention while managing fabrication complexity through parameter optimization rather than additional process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the creation of high-density, high-capacity memory devices with low read latency and efficient memory access, suitable for advanced computing applications, leveraging the unique properties of ferroelectric materials for improved memory performance.
Implementation Method 1
each memory transistor being a vertical channel-all-around ferroelectric transistor including a gate electrode, an annular channel layer, and an annular ferroelectric gate dielectric layer
Data Source
AI summary
A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.