3D Stacked FET Backside Source/Drain Formation at Reduced Pitch

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Solution Overview

Problem

The challenge in forming upper and lower source/drain regions in 3D-stacked semiconductor devices is exacerbated by the reduction in contact poly pitch, making it difficult to create vertically overlapping regions and BEOL/MOL structures, especially when supported by a backside power distribution network.

Innovation Solution

A semiconductor device and method where the lower source/drain region is formed in a backside process, involving the formation of a backside contact structure and isolation structure, with inner spacers and passivation layers, allowing for the creation of a 3D-stacked semiconductor device with improved source/drain region formation and reduced short-circuit risk.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If contact poly pitch is reduced to increase device density, then device density is improved, but forming upper and lower source/drain regions vertically overlapping each other becomes more difficult

Engineering Contradiction:
Improvedevice densityVSAvoidsource/drain region formation
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from conventional front-side source/drain formation to back-side formation, utilizing the vertical dimension and back-side access to create lower source/drain regions. This dimensional shift allows source/drain regions to be formed after channel structures are established, enabling vertical overlap without compromising manufacturability even at reduced pitch

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent performs preliminary actions by first forming channel structures (nanosheets or fins) and establishing the BSPDN backside contact structures before forming the lower source/drain regions. This preliminary structuring creates a template that guides subsequent source/drain formation, ensuring proper alignment and overlap at reduced pitch

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If contact poly pitch is reduced to increase device density, then device density is improved, but forming BEOL and MOL structures becomes more complicated

Engineering Contradiction:
Improvedevice densityVSAvoidBEOL and MOL structures
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the manufacturing process into distinct front-side and back-side operations. BEOL and MOL structures are formed on the front side while lower source/drain regions and backside contacts are formed on the back side. This segmentation allows each structure type to be optimized independently, reducing overall complexity despite high device density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By moving lower source/drain region formation to the back side, the patent creates spatial separation between front-side BEOL/MOL structures and lower source/drain regions. This dimensional separation reduces interference and complexity in forming both structure types simultaneously at reduced pitch

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If lower source/drain region is formed in front-side process, then manufacturing flow is conventional, but short-circuit risk increases

Engineering Contradiction:
Improvemanufacturing flowVSAvoidshort-circuit risk
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent inverts the conventional manufacturing sequence by forming lower source/drain regions on the back side after channel structures are formed, rather than forming them on the front side before channel structures. This inversion ensures that lower source/drain regions are formed in a controlled manner with proper isolation, reducing short-circuit risk while maintaining manufacturing feasibility

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent introduces backside isolation structures as intermediaries between lower source/drain regions and the substrate. These isolation structures prevent direct contact and potential short-circuits, while allowing the lower source/drain regions to be formed in a controlled backside process

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240413213A1Noble formation method of CMOS for 3D stacked FET with bspdn
Publication Date: 2024.12.12 SAMSUNG ELECTRONICS CO LTD
  • US20240413213A1 patent drawing
  • US20240413213A1 patent drawing
  • US20240413213A1 patent drawing

AI summary

Provided is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a 1st source/drain region connected to a 1st channel structure; a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure above the 1st channel structure; a backside contact structure on a bottom surface of the 1st source/drain region; and a backside isolation structure surrounding the backside contact structure, wherein the bottom surface of the 1st source/drain region is at a level below a top surface of the backside isolation structure.