3D FET Layout Using Vertical and Horizontal Channels
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Solution Overview
Problem
Existing two-dimensional (2D) semiconductor circuits face challenges in scaling as they enter single-digit nanometer fabrication nodes, leading to a desire for three-dimensional (3D) semiconductor circuits where transistors are stacked vertically to increase transistor density.
Innovation Solution
The development of Λ-3D fabrication techniques for semiconductor devices, which involve integrating both horizontal and vertical nanosheets, resulting in a L-shaped field-effect transistor (FET) structure. This architecture includes epitaxially grown semiconductor structures with specific doping levels and dielectric structures to form transistors with reduced parasitic resistances and capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 2D planar transistor scaling is continued, then transistor density per area increases, but manufacturing challenges and performance degradation worsen at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from 2D planar transistors to 3D vertically-stacked transistors, adding a vertical dimension to transistor arrangement. Multiple transistor layers are stacked above each other on the substrate, enabling increased transistor density without further scaling lateral dimensions, thereby avoiding the manufacturing challenges associated with single-digit nanometer node scaling.
2Quantity of substance
If transistor size is reduced to increase density, then more transistors fit in the same area, but parasitic resistances and capacitances increase
Solution Approach 1:
By stacking transistors vertically in 3D layers rather than arranging them in 2D planes, the patent increases transistor density while maintaining larger effective transistor dimensions within each layer. This vertical arrangement reduces the parasitic resistances and capacitances that plague scaled-down 2D transistors.
Solution Approach 2:
The patent divides the transistor structure into multiple discrete layers stacked vertically, with each layer containing transistors that can be independently optimized. This segmentation allows each transistor layer to maintain appropriate dimensions for low parasitics while the overall stack achieves high density.
3Quantity of substance
If 3D vertical stacking is implemented, then transistor density in volume increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements 3D vertical stacking of transistors with standardized layer structures, which increases volume density while managing complexity through repetitive modular layer design. Each layer follows a consistent structure that can be manufactured using adapted standard processes.
Solution Approach 2:
The patent employs universal layer structures that can serve multiple functions - transistor channels, isolation regions, and interconnect layers are designed with multi-functionality to reduce the number of distinct manufacturing steps required, thereby managing device complexity while achieving high density.
4Use of energy by moving object
If power consumption is reduced, then energy efficiency improves, but operating frequency may be compromised
Solution Approach 1:
The 3D vertically-stacked transistor architecture reduces power consumption through shorter carrier transport paths and reduced parasitic resistances and capacitances. The vertical channel structure enables efficient current flow while maintaining high operating frequencies, decoupling the power-frequency tradeoff that plagues 2D scaled transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The Λ-3D fabrication technique achieves a significant 30% reduction in power consumption at the same operating frequency, enhances transistor density, and improves overall performance by reducing parasitic resistances and capacitances.
Implementation Method 1
Each of the first semiconductor structure and the second semiconductor structure can be an epitaxially grown structure from the semiconductor substrate
Data Source
AI summary
Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device may include a semiconductor substrate including a first area and a second area; a first semiconductor structure disposed in the first area, vertically extending, and separated from the semiconductor substrate with a first dielectric structure interposed therebetween; a first transistor disposed around the first semiconductor structure, with the first semiconductor structure serving as a channel of the first transistor; a second semiconductor structure disposed in the second area, vertically extending, and in contact with the semiconductor substrate; and a second transistor disposed above the second semiconductor structure, with a third semiconductor structure laterally extending and serving as a channel of the second transistor.