3D Vertically-Integrated FETs for CMOS Area Reduction
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Solution Overview
Problem
The challenge in minimizing the total area of CMOS cell circuits in integrated circuits (ICs) is exacerbated by high congestion in metal interconnect layers, which limits the density and area efficiency of CMOS cell circuits.
Innovation Solution
The implementation of three-dimensional (3D) vertically-integrated Field-Effect Transistors (FETs) with vertical FET-to-FET interconnects, where a second FET channel structure is stacked above a first FET channel structure, reducing the need for horizontal vias and metal traces, thereby decreasing the footprint and congestion in metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional two-dimensional CMOS cell circuits are used, then the circuit layout is simple and easy to manufacture, but the total area occupied by the circuit is large due to high congestion in metal interconnect layers
Solution Approach 1:
The patent transitions from conventional two-dimensional planar CMOS cell circuits to three-dimensional vertically-integrated architectures. Multiple FETs are stacked vertically with channel structures extending in the vertical direction, allowing interconnects to route signals between vertically-separated transistor layers. This dimensional transition reduces horizontal footprint and metal interconnect congestion while maintaining circuit functionality.
2Area of stationary object
If the dimensions of CMOS cell circuits are minimized, then area efficiency is improved, but the density of metal traces increases causing congestion
Solution Approach 1:
By stacking FETs vertically and routing interconnects in the vertical dimension between transistor layers, the patent reduces the horizontal footprint of CMOS cell circuits without increasing metal trace density in any given horizontal plane. The vertical integration allows compact packaging while maintaining adequate spacing between interconnect elements.
3Area of stationary object
If more functionality is integrated in a smaller package, then the total IC area is reduced, but the congestion of metal traces in interconnect layers increases
Solution Approach 1:
The patent enables higher integration density by utilizing vertical stacking of FETs and three-dimensional interconnect routing. This allows more functional units to be packed into a smaller IC footprint by exploiting the vertical dimension, thereby reducing overall IC area without proportionally increasing metal trace congestion through efficient spatial utilization.
Data Source
AI summary
3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.