3D FET Source/Drain Isolation Using a Sacrificial SiGe Layer
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Solution Overview
Problem
Existing methods for manufacturing three-dimensional field-effect transistors (3D FETs) face challenges in vertically separating n-type (NMOS) and p-type (PMOS) transistors, due to tight process margins.
Innovation Solution
The method involves epitaxially growing source/drain regions of the lower field-effect transistor, depositing a sacrificial silicon-germanium (SiGe) layer, epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer, and selectively etching the sacrificial layer to create a gap, which is then filled with an oxide layer to isolate the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional manufacturing methods are used for 3D FETs, then the process is simpler, but the vertical separation between NMOS and PMOS transistors is challenging due to tight process margins
Solution Approach 1:
A sacrificial layer is deposited on the source/drain regions before epitaxial growth of the upper transistor. This preliminary action creates a controlled interface that enables precise vertical separation. The sacrificial layer serves as a temporary structure that defines the separation gap, allowing tight process control during subsequent etching operations.
Solution Approach 2:
The sacrificial layer acts as an intermediary element between the lower and upper transistors. It provides a controlled interface that mediates the vertical separation process, enabling precise gap formation between source/drain regions. The intermediary layer is later removed to create the final separation, having served its purpose during the separation process.
2Reliability
If the sacrificial layer thickness is increased to ensure proper separation, then separation reliability improves, but the oxide layer thickness requirement increases
Solution Approach 1:
The method optimizes the thickness parameter of the sacrificial layer to be less than the source/drain region thickness. This parameter change ensures that when the sacrificial layer is removed, a controlled gap remains that is sufficient for reliable separation but does not require excessive oxide layer thickness. The parameter optimization balances separation reliability with minimal oxide requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively isolates the source/drain regions of the lower and upper field-effect transistors, improving the controllability and quality of the source/drain regions of the upper field-effect transistor while maintaining proper vertical separation.
Implementation Method 1
epitaxially growing source/drain regions of the lower field-effect effect transistor
Implementation Method 2
selectively etching the sacrificial layer to form a gap
Implementation Method 3
depositing an oxide layer in the gap
Data Source
AI summary
A method of manufacturing a three-dimensional field-effect transistor including an upper field-effect transistor stacked on a lower field-effect transistor. The method includes epitaxially growing source/drain regions of the lower field-effect effect transistor, growing a sacrificial layer on an upper surface of the source/drain regions, and epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer. The sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor. The method also includes selectively etching the sacrificial layer to form a gap between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor, and depositing an oxide layer in the gap.