3D FET Switch Array Layout Using Hybrid Bonded IC Stacks
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Solution Overview
Problem
Conventional 2-D IC dies face challenges in reducing their planar area while maintaining high performance for RF circuitry, particularly in FET switch arrays, due to parasitic resistances, capacitances, and inductances, which affect power efficiency and linearity.
Innovation Solution
The development of 3-D integrated circuit structures using hybrid bonding interconnects (HBI) that stack and bond IC wafers/dies, interleaving FET cells and buses to reduce parasitic resistance and area, with conductive vias and traces connecting HBI plugs between wafers/dies, enabling efficient RF signal routing and reduced planar footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If 2-D planar IC die structure is used, then manufacturing and routing are simpler, but planar area consumption increases and parasitic resistances/capacitances/inductances affect performance
Solution Approach 1:
The patent transitions from a conventional 2-D planar IC die structure to a 3-D stacked structure by bonding multiple IC dies vertically. This dimensional change allows circuit elements to be arranged in three dimensions rather than confined to a single plane, significantly reducing the planar footprint while maintaining manufacturing processes adapted from conventional 2-D techniques.
Solution Approach 2:
The patent divides the IC circuit into multiple separate IC dies that can be manufactured independently using conventional 2-D processes. Each die contains portions of the overall circuit, and these segmented dies are then bonded together vertically to form the complete 3-D integrated circuit, combining manufacturing simplicity with reduced planar area.
2Productivity
If more transistors are added to increase functionality, then electronic performance improves, but planar footprint increases
Solution Approach 1:
By stacking IC dies vertically in three dimensions, the patent enables increased transistor count and electronic functionality without proportionally increasing the planar footprint. The vertical stacking allows circuit elements to be arranged in multiple layers, effectively multiplying the functional capacity within the same planar area.
Solution Approach 2:
The patent combines multiple IC dies containing transistor circuits into a single integrated 3-D structure through bonding. This merging of multiple functional blocks vertically allows the system to achieve higher overall functionality while maintaining a compact planar footprint, as the combined functionality is achieved through vertical integration rather than horizontal expansion.
3Area of stationary object
If 3-D stacked structure is used, then planar area is reduced, but parasitic resistances and bonding complexity increase
Solution Approach 1:
The patent segments the overall circuit into multiple IC dies with well-defined interfaces, allowing each die to be manufactured and tested independently before bonding. This segmentation reduces bonding complexity by standardizing the interfaces and connection points between dies, making the 3-D stacking process more manageable despite the increased number of components.
4Ease of manufacture
If conventional 2-D structure is used, then routing is simpler, but parasitic resistances and capacitances degrade RF performance
Solution Approach 1:
The patent uses vertical stacking to create three-dimensional routing paths that reduce the horizontal distance signals must travel across the IC. This dimensional change shortens interconnect lengths and reduces parasitic resistances and capacitances that degrade RF performance, while the bonding interfaces provide well-defined routing connections between stacked dies.
Data Source
AI summary
Three-dimensional (3-D) integrated circuit structures and circuits that enable high performance FET switch arrays while consuming less planar area than conventional 2-D IC dies. In one embodiment, an integrated FET switch circuit includes a first wafer/die including a first set of groups of FET cells, and a second wafer/die joined to the first wafer/die through hybrid bonding interconnects and including a second set of groups of FET cells, wherein a first side drain bus of each group in the first wafer/die is connected through the hybrid bonding interconnects to a second side source bus of a first corresponding group in the second wafer/die; and wherein a second side source bus of each group in the first wafer/die is connected through the hybrid bonding interconnects to a first side drain bus of a second corresponding group in the second wafer/die.