Multilayer 3D Film Package With Cavity Stacking for Low-Profile Electronics
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Solution Overview
Problem
Existing 3D integration techniques for electronic components face challenges such as high integration density, complexity, susceptibility to breakage, and poor heat dissipation, leading to increased costs and inefficiencies in producing three-dimensional packages.
Innovation Solution
A multilayer 3D film package is proposed, comprising vertically stacked film substrates with cavities in one substrate to accommodate protruding components, using electrically insulating materials like polyimide or glass, and connected via conductive vias for efficient heat dissipation and reduced package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D integration techniques using TSV (through silicon via) are employed, then vertical connection of components is achieved, but the manufacturing complexity increases and production costs rise
Solution Approach 1:
The patent changes the substrate material parameter from silicon to glass interposer, and modifies the via structure by eliminating the need for electrical insulation coatings. This parameter change simplifies the manufacturing process while maintaining vertical connection functionality, directly resolving the contradiction between reliability and manufacturing complexity
Solution Approach 2:
The invention extracts and removes the complex insulation requirement from the TSV structure by using glass interposers that inherently provide electrical insulation. This eliminates the need for additional insulation layers and complex process steps, reducing manufacturing complexity while preserving the vertical connection capability
2Device complexity
If glass interposer wafers are used to eliminate insulation requirements, then manufacturing complexity is reduced, but the thin glass wafers become highly susceptible to breakage
Solution Approach 1:
The patent applies beforehand cushioning by providing mechanical support structures and optimized handling procedures for the thin glass interposer wafers during the manufacturing process. This preemptive measure protects the fragile glass wafers from breakage while allowing the simplified manufacturing approach to proceed
Solution Approach 2:
The invention utilizes the inherent properties of thin glass films as interposers, leveraging their flexibility and thinness to achieve the desired electrical insulation and mechanical support functions while managing their susceptibility to breakage through careful process design
3Ease of manufacture
If chip components are stacked on standard PCB material, then assembly is simplified, but the package height increases and heat dissipation is compromised
Solution Approach 1:
The patent employs thin film substrates instead of conventional thick PCB materials for stacking chip components. This thin film approach maintains assembly simplicity while dramatically reducing the overall package height and improving heat dissipation pathways, directly resolving the contradiction between ease of manufacture and package height
4Length of stationary object
If thin film substrates are used to reduce package height, then package height is reduced, but the ability to accommodate protruding components is limited
Solution Approach 1:
The patent applies local quality by creating localized cavity structures at specific positions on the thin film substrates where protruding components need to be accommodated. The majority of the substrate remains thin for low package height, while localized regions provide the necessary depth for protruding components, thus resolving the contradiction between package height and adaptability
Data Source
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AI summary
The invention relates to a multi-layered 3D foil package (100) and a method for producing such a multi-layered 3D foil package (100).The 3D film package (100) comprises a film substrate stack (150) with at least two film layers (E1, E2), wherein a first electrically insulating film substrate (110) is arranged in a first film layer (E1), and wherein a second electrically insulating film substrate (120) is arranged in a second film layer (E2), wherein the first film substrate (110) has a first main surface region (111) on which at least one functional electronic component (113) is arranged, and wherein the second film substrate (120) has a cavity (124) with at least one opening in the second main surface region (122), and wherein the film substrates (110, 120) are arranged one above the other within the film substrate stack (150) such that the functional electronic component (113) arranged on the first film substrate (110) is within the cavity in the The second foil substrate (120) is arranged in the cavity (124).