3D Fin Tunneling Field Effect Transistor Drive Current
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Solution Overview
Problem
Tunneling field effect transistors (TFETs) face poor performance in drive current due to a limited effective channel width for band-to-band tunneling, which has led manufacturers to shy away from using TFET technology.
Innovation Solution
The method involves forming gate structures over semiconductor fins with varying pitches, recessing the fin between the gate structures, and depositing dielectric layers to create asymmetrical source and drain regions that occupy the entire width and height of the fin, increasing the effective channel width and improving drive current without the need for lithography or ion implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TFET structures are used, then the device has intrinsically better subthreshold slope and scaling capability than MOSFETs, but the drive current is poor due to limited effective channel width
Solution Approach 1:
The patent transitions from a planar 2D channel structure to a three-dimensional fin structure with multiple pitches. The fin extends vertically from the substrate, creating additional spatial dimensions for charge carrier transport. This 3D configuration increases the effective channel width while maintaining the tunneling mechanism that provides excellent subthreshold slope, thereby resolving the contradiction between reliability and drive current performance
Solution Approach 2:
The channel region is segmented into multiple sections with different pitch dimensions (first pitch, second pitch, third pitch). Each pitch section contributes differently to the effective channel width, allowing optimization of both tunneling efficiency and drive current. The segmentation enables the device to maintain good subthreshold slope in some regions while maximizing drive current in others
2Power
If the effective channel width is increased to improve drive current, then the device complexity increases due to multiple dielectric layers and selective etching processes
Solution Approach 1:
Dielectric layers are deposited and patterned in advance to define the pitch regions before fin formation and doping. The first, second, and third dielectric layers are sequentially deposited with specific patterns that pre-establish the regions where source and drain regions will later be formed. This preliminary structuring simplifies subsequent processing steps by providing self-aligned guides for selective etching and doping operations
Solution Approach 2:
Multiple dielectric layers serve as intermediary structures that mediate between the gate structures and the fin regions. These dielectric layers with different pitches act as spacers and定义 boundaries that control the formation of source and drain regions. The intermediary dielectric structures enable precise spatial control of doping regions without requiring complex lithography steps, thus managing fabrication complexity while achieving increased effective channel width
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the subthreshold slope, scaling capability, and drive current of TFETs, providing a 3D structure that surpasses conventional MOSFETs in performance by increasing the effective channel width for band-to-band tunneling, thus overcoming the limitations of TFETs.
Implementation Method 1
depositing dielectric layers to create asymmetrical source and drain regions
Data Source
AI summary
A method for forming a tunneling field effect transistor includes forming gate structures over a semiconductor fin on a substrate having at least two pitches between the gate structures and recessing the fin between the gate structures. A first dielectric layer is deposited over the fin to fill in a first gap between the gate structures having a smaller pitch therebetween. A second gap between the gate structures having a larger pitch is filled with a second dielectric layer. The first gap is opened by etching the first dielectric layer while the second dielectric layer protects from opening the second gap. A source region is formed on the fin in the first gap. A dielectric fills the source region in the first gaps. The second gap is opened by etching the second dielectric layer and the first dielectric layer. A drain region is formed on the fin in the second gap.