3D Laminated Flash Memory Cell Structure for Threshold Voltage Stability
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Solution Overview
Problem
Current dynamic flash memory devices face challenges in achieving high capacity and cost-effectiveness while maintaining reliable operation and data retention due to fluctuations in the potential of the floating cell channel, which affects the operation margin and retention characteristics.
Innovation Solution
A three-dimensional laminated memory device structure is developed, where semiconductor layers and insulating layers are alternately laminated on a substrate, forming memory cells with specific impurity regions and gate conductor layers to stabilize the threshold voltage and enhance data retention, allowing for increased capacity without the need for variable resistance elements or capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased using conventional two-dimensional structures, then storage density improves, but device area and cost increase
Solution Approach 1:
The invention transitions from a conventional two-dimensional memory structure to a three-dimensional stacked structure. Multiple memory cell layers are stacked vertically, allowing significant increase in memory capacity without proportionally increasing the device footprint area, thereby improving storage density and reducing cost per bit
2Quantity of substance
If variable resistance elements or capacitors are used to increase capacity, then storage density improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The invention uses a uniform semiconductor material system (silicon-based) throughout the memory structure, including the charge trap layer and cell channels. This homogeneous material approach simplifies manufacturing processes and reduces device complexity compared to using heterogeneous materials like variable resistance elements or capacitors, while still achieving high capacity through the 3D stacked architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases memory capacity, reduces bit unit cost, and improves operational margins by stabilizing the threshold voltage and enhancing data retention, while also reducing power consumption and increasing memory operation speed.
Implementation Method 1
by an impact ionization phenomenon due to a current between the source and drain of an N-channel MOS transistor, part or all of the positive holes are retained in the channel to write logical memory data '1'
Implementation Method 2
a first gate insulating layer in contact with a side surface of the first semiconductor layer opposite to a side surface thereof in contact with the second semiconductor layer and a first gate conductor layer in contact with the first gate insulating layer
Data Source
AI summary
A three-dimensional laminated dynamic flash memory device includes a plurality of laminated memory cells on a substrate. In a first memory cell, a semiconductor layer is made of a first semiconductor layer extending in a first direction and a second semiconductor layer connected to one side of the first semiconductor layer and extending in a second direction orthogonal to the first direction in a plan view. The first memory cell includes first and second impurity regions in contact with both ends of the first semiconductor layer in the first direction in the plan view, a third impurity region in contact with an end of the second semiconductor layer opposite to an end thereof in contact with the first semiconductor layer in the plan view, a first gate insulating layer in contact with a side surface of the first semiconductor layer and a first gate conductor layer in contact with the first gate insulating layer in the plan view, and second and third gate conductor layers in contact with respective side surfaces of second and third gate insulating layers in contact with both side surfaces of the second semiconductor layer in the plan view.