3D AND Flash Memory Channel Ring Isolation for Lower Leakage
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Solution Overview
Problem
Current 3D AND flash memory devices face challenges in reducing leakage current, which affects their performance and efficiency.
Innovation Solution
The 3D AND flash memory device is designed with a gate stack structure and channel stack structure where channel rings are physically separated by insulating layers, allowing the gate layer to control channel regions effectively, reducing leakage current and enhancing the current ratio between on and off states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel regions are continuously connected in 3D AND flash memory device, then device integration and area utilization are improved, but leakage current increases
Solution Approach 1:
The channel stack structure is divided into multiple channel rings that are separated from each other by insulating layers. This segmentation breaks the continuous channel path into discrete segments, allowing the device to maintain high integration through vertical stacking while preventing leakage current by isolating adjacent channel regions electrically.
Solution Approach 2:
Insulating layers are introduced as intermediary structures between adjacent channel rings. These insulating layers act as mediators that physically separate and electrically isolate the channel regions, enabling the device to achieve both high integration density and low leakage current by preventing direct electrical connection between neighboring channels.
2Object-generated harmful factors
If channel regions are separated by insulating layers, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The patent transitions from a planar channel structure to a vertical 3D stacked structure with channel rings arranged in multiple layers. By utilizing the vertical dimension, the device achieves separation of channel regions through insulating layers while maintaining compact footprint, thus reducing leakage current without proportionally increasing overall device complexity.
Solution Approach 2:
The channel rings are nested within the gate stack structure, with insulating layers integrated between the channel rings and gate layers. This nested arrangement allows multiple functional layers to be compactly organized in a vertical hierarchy, reducing leakage current through separation while minimizing the increase in structural complexity through efficient space utilization.
Data Source
AI summary
A 3D AND flash memory device includes a gate stack structure, a channel stack structure, a source pillar and a drain pillar, and a plurality of charge storage structures. The gate stack structure is located on the dielectric substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel stack structure extends through the gate stack structure. The channel stack structure includes a plurality of channel rings spaced apart from each other. The source pillar and the drain pillar are located in the channel stack structure and are respectively electrically connected to the plurality of channel rings. The plurality of charge storage structures are located between the plurality of gate layers and the plurality of channel rings.