3D Flash Memory Channel Segmentation for Bulk Erase

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Solution Overview

Problem

Existing three-dimensional flash memory devices face challenges in supporting bulk erase operations due to increased channel layer length, which reduces cell current and deteriorates cell characteristics, and the complexity of wiring processes increases with the addition of intermediate wiring layers.

Innovation Solution

A three-dimensional flash memory device structure incorporating an intermediate wiring layer that can be reconfigured as either a source or drain electrode, with connectors connecting divided channel layers, and a manufacturing method that forms an inversely stepwise shape for the wiring layers to improve integration and simplify the wiring process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the channel layer length is increased to support bulk erase operation, then the bulk erase capability is improved, but the cell current decreases and cell characteristics deteriorate

Engineering Contradiction:

Improvebulk erase capabilityVSAvoidcell current

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The channel layer is divided into multiple segments by inserting intermediate wiring layers at different heights. This segmentation allows the channel layer to be divided into upper and lower portions, enabling bulk erase operation while maintaining sufficient channel length for good cell characteristics in each segment.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Intermediate wiring layers are inserted at different vertical heights within the channel layer, utilizing the vertical dimension to divide the channel. This allows the channel to be segmented without reducing the overall vertical extent, maintaining bulk erase capability while improving cell characteristics through reduced current path length in each segment.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If intermediate wiring layers are added to divide the channel layer, then cell current and cell characteristics are improved, but the wiring process complexity increases

Engineering Contradiction:

Improvecell characteristicsVSAvoidwiring process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The wiring structure is segmented into intermediate wiring layers inserted at different heights, with connectors forming inversely stepwise shapes. This segmentation allows independent formation of each wiring layer, simplifying the manufacturing process while achieving the goal of dividing the channel layer.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The connectors forming the intermediate wiring layers have inversely stepwise shapes, where the wiring layers are formed in reverse order of their final positions. This inversion approach simplifies the manufacturing process by allowing each wiring layer to be formed independently without complex alignment requirements.

Inventive Principle:

Principle #13The other way round (Inversion)

3Adaptability or versatility

If intermediate wiring layers are added to divide the channel layer, then bulk erase operation is supported, but the device structure becomes more complex

Engineering Contradiction:

Improvebulk erase operation supportVSAvoiddevice structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The intermediate wiring layers serve multiple functions: they divide the channel layer to enable bulk erase operation, act as source or drain electrodes for memory cells, and provide structural support. This multi-functionality reduces the need for separate components, simplifying the overall device structure despite the added complexity of intermediate layers.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The intermediate wiring layers are configured to be selectively used as either source or drain electrodes depending on the operational mode. This dynamic configurability allows the same structure to serve different functions, reducing the need for additional dedicated structures and simplifying the overall device architecture.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11844215B2Three-dimensional flash memory device supporting bulk erase operation and manufacturing method therefor

Publication Date: 2023.12.12 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided are a three-dimensional flash memory device supporting a bulk erase operation and a method of manufacturing the three-dimensional flash memory device. The three-dimensional flash memory device supporting a bulk erase operation includes: a string including a channel layer extending in one direction and a plurality of electrode layers stacked vertically with respect to the channel layer; an upper wiring layer on the string; at least one intermediate wiring layer arranged between the plurality of electrode layers through the channel layer in an intermediate region of the string; a lower wiring layer under the string; and at least one connector arranged in the at least one intermediate wiring layer and connecting, to each other, at least two channel layers divided by the at least one intermediate wiring layer.