3D Flash Memory COP Structure With Common Source Line Integration
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Solution Overview
Problem
Conventional 3D flash memory technologies face challenges in reducing manufacturing costs, simplifying layout design, effectively using area, and supporting bulk erasing operations due to complex processes and structural limitations, particularly in the COP structure where source lines for memory cell strings and peripheral circuits are distinct and isolated from the substrate.
Innovation Solution
Implementing a common source line for both memory cell strings and peripheral circuit transistors, and a connecting part to transmit bulk erasing voltage to memory cell strings, which are integrally formed through a single process, and optimizing wordline control lines to share contacts between memory cell arrays, reducing the complexity and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate source lines are used for memory cell strings and peripheral circuit transistors, then the COP structure can be implemented, but manufacturing costs increase and layout design becomes complex
Solution Approach 1:
The patent merges the source line for memory cell strings with the source lines for peripheral circuit transistors into a single common source line. This consolidation eliminates the need for separate source lines, thereby reducing manufacturing costs and simplifying layout design while maintaining the COP structure functionality.
Solution Approach 2:
The common source line serves multiple functions: it acts as the source line for memory cell strings and simultaneously as the source line for peripheral circuit transistors. This multi-functional design reduces the total number of components and interconnections, leading to lower manufacturing costs and simpler layout design.
2Ease of manufacture
If the memory cell string is isolated from the substrate by the insulating layer, then the COP structure is maintained, but bulk erasing operation cannot be supported
Solution Approach 1:
The common source line acts as an intermediary conductive path that bridges the isolated memory cell string and the substrate. It transmits the bulk erasing voltage from the substrate to the memory cell string through the insulating layer, enabling bulk erasing operation without compromising the COP structure's insulating isolation.
Solution Approach 2:
The common source line performs dual functions: it serves as the electrical source for memory cell strings and simultaneously as the voltage transmission path for bulk erasing operations. This multi-functionality enables bulk erasing support while maintaining the structural isolation required by the COP architecture.
3Ease of manufacture
If distinct source lines are manufactured through different processes, then the COP structure functionality is achieved, but manufacturing costs increase
Solution Approach 1:
The patent combines the manufacturing processes for the memory cell string source line and peripheral circuit source lines into a single unified process. The common source line is formed through one set of deposition and patterning steps, eliminating the need for separate manufacturing processes and reducing overall process complexity and costs.
Data Source
AI summary
A three-dimensional flash memory for promoting integration, and a manufacturing method therefor are disclosed. The three-dimensional flash memory to which a cell on peripheral circuit (COP) structure is applied comprises: a substrate having at least one transistor of a peripheral circuit, formed according to the COP structure; at least one memory cell string formed to extend in one direction above the at least one transistor; and a common source line commonly used by means of the at least one transistor and the at least one memory cell string.