3D Flash Memory Programming with Dynamic ISPP and Ferroelectric ONO

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Solution Overview

Problem

Existing ISPP schemes for three-dimensional flash memory face limitations in maintaining program characteristics due to nitride trap degradation, increased program voltage burden on circuits, and limited memory window capacity, especially with high integration and multi-level data storage needs.

Innovation Solution

Implementing an improved ISPP scheme with variable step voltages, applying negative and positive voltages to bit lines and back gates, and utilizing charge trap nitride and ferroelectric layers for data storage to enhance cell current and expand memory windows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a high program voltage is applied to increase program operation speed, then program operation speed is improved, but circuit burden increases and memory reliability deteriorates

Engineering Contradiction:

Improveprogram operation speedVSAvoidmemory reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The program operation is divided into multiple steps with incremental voltage increases. Instead of applying a single high voltage, the method applies a sequence of progressively higher voltages (Vpgm1, Vpgm2, Vpgm3, etc.), where each step increases by a fixed step voltage ΔV. This segmentation allows the program operation to achieve high speed while distributing the voltage stress across multiple smaller increments, reducing peak circuit burden and improving reliability.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If the step voltage is increased to expand memory window for multi-level data storage, then memory window capacity is improved, but program characteristic degradation due to nitride trap worsens

Engineering Contradiction:

Improvememory window capacityVSAvoidprogram characteristic

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The step voltage ΔV is made dynamic rather than fixed. The method adjusts the step voltage based on the current program voltage level and the desired memory window expansion. As the program voltage increases to accommodate multi-level data storage requirements, the step voltage is dynamically adjusted to prevent excessive nitride trap accumulation, thereby maintaining program characteristic while expanding memory window capacity.

Inventive Principle:

Principle #15Dynamics

3Quantity of substance

If the number of layers and degree of integration are increased to improve storage capacity, then storage capacity is improved, but program operation speed and cell current decrease

Engineering Contradiction:

Improvestorage capacityVSAvoidprogram operation speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The method changes the voltage parameters adaptively based on the number of layers and integration degree. As the flash memory structure becomes more complex with increased layers and integration, the program voltage sequence and step voltage are adjusted to compensate for the increased electrical resistance and reduced cell current. This parameter adaptation maintains program operation speed despite the increased structural complexity.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution addresses nitride trap degradation, reduces circuit burden, improves memory reliability, and expands memory window capacity for multi-level data storage in three-dimensional flash memory.

Implementation Method 1

utilizing charge trap nitride and ferroelectric layers for data storage

Methodology Applied

Scientific EffectCharge trap:

Implementation Method 2

utilizing charge trap nitride and ferroelectric layers for data storage

Methodology Applied

Scientific EffectFerroelectric effect:

Implementation Method 3

A flash memory device that is an electrically erasable programmable read only memory (EEPROM) controlling the data input/output through the F-N (Fowler-Nordheim) tunneling or the hot electron injection

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Implementation Method 4

Methodology Applied

Scientific EffectHot electron injection:

Data Source

PatentUS12475951B2Method for operating three-dimensional flash memory

Publication Date: 2025.11.18 INDUSTRY UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY

AI summary

Provided is a method for operating a program of a three-dimensional flash memory. A program voltage has a value obtained by adding a step voltage to a previous program voltage applied in a previous program operation, and the step voltage is increased as a program operation is repeated. Also, the program operation is performed on a target memory cell by applying a negative voltage to a bit line of a selected cell string and applying the program voltage to a selected word line. In addition, tunneling oxide-charge trap nitride-blocking oxide (ONO) formed surrounding a vertical channel pattern is included, and at least one of a tunneling oxide layer or a blocking oxide layer of the ONO is formed of a ferroelectric material.