3D Inverted Flash Memory Structure With Lateral Floating Gate
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Solution Overview
Problem
Existing 3D inverted flash memory structures face challenges in achieving high storage density and parameter tuning due to difficulties in integrating a vertically-stacked architecture, particularly in inverted flash memory IC structures.
Innovation Solution
A laterally-extending floating gate structure is employed in a 3D inverted flash memory IC device, allowing for vertical stacking of multiple transistors while enabling parameter tuning through adjustments in control and floating gate sizes and tunnel dielectric thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertically-stacked architecture is implemented in 3D inverted flash memory, then storage density is enhanced, but integration difficulty and manufacturing complexity increase
Solution Approach 1:
The patent inverts the conventional flash memory structure by positioning the tunnel oxide between the floating gate and control gate instead of between the floating gate and channel. This inversion simplifies the vertical stacking process and enables easier integration of multiple transistors in a 3D architecture, thereby resolving the contradiction between enhanced storage density and integration difficulty
Solution Approach 2:
The patent transitions from a planar 2D structure to a three-dimensional vertically-stacked architecture, stacking multiple transistors vertically to increase storage density while managing complexity through the inverted structure design that facilitates integration
2Ease of manufacture
If conventional flash memory structure is used, then fabrication is straightforward, but parameter tuning capability is limited
Solution Approach 1:
The inverted flash memory structure enables parameter tuning by allowing adjustment of control gate and floating gate dimensions, as well as tunnel oxide thickness, to optimize memory window and operational characteristics while maintaining fabrication feasibility through standard semiconductor processing techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure provides a large memory window and facilitates efficient programming, erasing, and reading operations, while enabling vertical stacking of transistors, thus enhancing storage density and operational flexibility.
Implementation Method 1
a tunnel dielectric between the floating gate and the control gate
Data Source
AI summary
Some embodiments relate to an integrated circuit (IC) device that includes a conductive layer; a dielectric structure disposed over the conductive layer; a first conductive structure disposed within the dielectric structure and separated from the conductive layer; a semiconductor structure disposed within the dielectric structure and extending vertically from the conductive layer to the first conductive structure; a first dielectric element disposed within the dielectric structure and extending vertically from the conductive layer alongside the semiconductor structure; a conductive element disposed within the dielectric structure between and separated from the conductive layer and the first conductive structure, and extending laterally from the first dielectric element; a second conductive structure disposed within the dielectric structure and extending vertically from near a surface of the conductive element opposite the conductive layer; and a second dielectric element disposed within the dielectric structure and at least partially surrounding the second conductive structure.