3D Flash Memory MAC Architecture With Current Summation
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Solution Overview
Problem
Traditional memory devices used for multiply accumulate (MAC) operations in AI applications are slow due to large data movements, and existing 3D memory technologies face challenges in improving MAC operations without increasing circuit area.
Innovation Solution
A memory device with a memory array, local and global signal line decoders, and conversion units that perform MAC operations by inputting inputs via word lines, summing cell currents on signal lines, and converting them into an output, utilizing a 3D AND type flash memory structure with single-level storage cells and optimized circuit design to achieve efficient MAC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional ALU or FPU are used to perform MAC operations by accessing data from memories, then the operation can be completed, but the operation speed becomes slow due to large data movements between memories
Solution Approach 1:
The patent merges the memory storage function with the MAC computation function into a single integrated structure. Memory cells store weights and directly generate currents proportional to weight×input products, eliminating the need for separate ALU/FPU units and reducing data movement between memory and computation units.
Solution Approach 2:
The patent replaces the mechanical/data-movement-based computation system (reading weights from memory, transporting to ALU, performing multiplication) with a physics-based system where currents naturally flow through memory cells according to Ohm's law, with current magnitude automatically representing the product of weight and input voltage.
2Quantity of substance
If 3D stacking is used to improve memory storage density, then storage density increases, but the circuit area may increase which is not desirable for MAC operations
Solution Approach 1:
The patent makes memory cells perform multiple functions: they serve as both storage elements (holding weight values) and computation elements (generating MAC products). This multi-functionality allows the same physical memory structure to provide both high storage density and MAC computation capability without requiring additional dedicated computation circuitry.
Solution Approach 2:
The patent utilizes 3D vertical stacking to increase the number of memory cells per unit area. By stacking multiple memory layers vertically, the system achieves high storage density and corresponding MAC capability without increasing the horizontal footprint of the circuit.
3Measurement precision
If more second signal lines are coupled to the same conversion unit to present higher x-level weights, then the weight precision improves, but the circuit complexity increases according to Q=2^x-1
Solution Approach 1:
The patent segments the signal lines into multiple groups, with each group coupled to a separate conversion unit. This segmentation allows the system to handle high-precision weights by distributing the signal lines across multiple conversion units rather than requiring all signal lines to be coupled to a single conversion unit, thereby reducing the complexity burden on any single conversion unit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed MAC operations with reduced circuit area and cost, achieving up to 6.7 Tera Operations Per Second (TOPS) with improved performance characteristics such as low random telegraph noise and reduced read-disturbance, while maintaining a simple structure.
Implementation Method 1
the memory cells output a plurality of cell currents to the second signal lines based on the weights of the memory cells
Implementation Method 2
the cell currents on each of the second signal lines are summed into a plurality of signal line currents
Implementation Method 3
the conversion unit converts the global signal line current from the local signal line decoder into an output, wherein the output represents a MAC operation result
Data Source
AI summary
A memory device and an operation method thereof are provided. The operation method comprises: in performing a multiply accumulate (MAC) operation, inputting a plurality of inputs into a plurality of memory cells via a plurality of first signal lines; outputting a plurality of cell currents from the memory cells to a plurality of second signal lines based on a plurality of weights of the memory cells; summing the cell currents on each of the second signal lines into a plurality of signal line currents: summing the signal line currents into a global signal line current: and converting the global signal line current into an output, wherein the output represents a MAC operation result of the inputs and the weights.