3D Dynamic Flash Memory Multi-Cell Structure for Lower Leakage
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Solution Overview
Problem
Current dynamic random-access memory (DRAM) technologies face challenges with increased leakage currents, power consumption, and decreased retention times, especially in high-temperature operations, and there is a need for capacitor-free solutions to enhance storage density and reduce refresh rates.
Innovation Solution
A three-dimensional (3D) memory device design featuring monolithic vertical pillars and insulating layers with a control gate structure, allowing for multi-state logic and independent addressing of memory cells, which decreases leakage current, power consumption, and increases charge retention times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 1T1C DRAM is used to increase storage density, then storage density is improved, but leakage current increases and retention time decreases
Solution Approach 1:
The patent removes the capacitor component from the memory cell, transitioning from 1T1C architecture to capacitor-free 1T DRAM. This extraction eliminates the capacitor-related leakage current while maintaining storage functionality through alternative charge storage mechanisms in the channel region.
Solution Approach 2:
The patent changes the physical parameters of the transistor by reducing channel width and adjusting doping concentrations to create strong inversion conditions. These parameter changes enable sufficient charge storage in the channel to maintain data retention without requiring a capacitor.
2Quantity of substance
If 1T1C DRAM is used to increase storage density, then storage density is improved, but power consumption increases
Solution Approach 1:
By removing the capacitor from the memory cell structure, the patent eliminates the energy required for capacitor charging and discharging operations, thereby reducing overall power consumption while maintaining storage density through the simplified 1T architecture.
3Quantity of substance
If 1T1C DRAM is used to increase storage density, then storage density is improved, but retention time decreases
Solution Approach 1:
The patent optimizes transistor parameters including channel width, doping concentration, and gate voltage to create strong inversion conditions that enhance charge storage capability in the channel region, thereby improving retention time without requiring a capacitor.
4Object-generated harmful factors
If capacitor-free 1T DRAM is used to decrease leakage current, then leakage current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies precise parameter ranges for channel width (5nm to 20nm) and doping concentrations to achieve strong inversion conditions. These controlled parameter changes enable reduced leakage current while providing clear manufacturing guidelines to manage precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3D memory device achieves increased storage density, multi-state logic capabilities, reduced leakage current, decreased power consumption, and lower refresh rates, improving operational efficiency and stability, especially at high temperatures.
Implementation Method 1
The first pillar can be configured to store a first electrical charge. The second pillar can be configured to store a second electrical charge.
Implementation Method 2
the control gate can invert a channel in the recessed pillar to form the charge (e.g., hole) isolation region
Data Source
AI summary
A three-dimensional (3D) memory device includes a first memory cell, a second memory cell, a control gate between the first and second memory cells, a top contact coupled to the first memory cell, and a bottom contact coupled to the second memory cell. The first memory cell can include a first pillar, a first insulating layer surrounding the first pillar, a first gate contact coupled to a first word line, and a second gate contact coupled to a first plate line. The second memory cell can include a second pillar, a second insulating layer surrounding the second pillar, a third gate contact coupled to a second word line, and a fourth gate contact coupled to a second plate line. The 3D memory device can utilize dynamic flash memory (DFM), increase storage density, provide multi-cell storage, provide a three-state logic, decrease leakage current, increase retention time, and decrease refresh rates.