3D Flash Memory With P-Type Source/Drain Pillars
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Solution Overview
Problem
Current 3D flash memory technologies face challenges in achieving high integration and efficient operation speed while minimizing the risk of over erasing, which affects data storage reliability and processing time.
Innovation Solution
The proposed 3D flash memory design includes a gate stack structure, annular channel pillar, and source/drain pillars with a charge storage structure between gate layers and the channel pillar, allowing for high integration and efficient operation with P-type doped source/drain pillars that eliminate the concern of over erasing, enabling one-shot pulse erase operations and reduced processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D flash memory structures are used, then integration can be achieved, but over erasing occurs affecting data storage reliability
Solution Approach 1:
The patent applies local quality by using P-type doped source/drain pillars specifically in regions where over-erasing occurs, while maintaining N-type doping in other critical regions. This localized doping strategy addresses the over-erasing problem in specific areas without compromising the overall memory operation, thereby improving data storage reliability while eliminating the harmful over-erasing effect.
Solution Approach 2:
The patent changes the doping type parameter from conventional N-type to P-type in the source/drain pillars. This parameter change fundamentally alters the electrical characteristics of the memory cell, enabling one-shot pulse erase operations that completely eliminate over-erasing issues and improve data storage reliability through clearer threshold voltage distinctions.
2Productivity
If conventional flash memory operation is used, then data can be stored, but processing time is increased
Solution Approach 1:
The patent implements periodic action through one-shot pulse erase operations that use precisely timed voltage pulses to erase memory cells. This approach replaces continuous or multi-step erase processes with single, periodic pulses, significantly reducing processing time while maintaining complete erase effectiveness and improving overall productivity.
Solution Approach 2:
By changing the doping parameter to P-type, the patent enables faster erase operations through one-shot pulses. The altered electrical characteristics allow for quicker charge removal and threshold voltage switching, directly reducing processing time and increasing memory operation speed.
3Area of stationary object
If integration is increased, then area utilization improves, but over erasing risk increases
Solution Approach 1:
The patent maintains high area utilization through compact 3D flash memory structure while applying P-type doping locally to counteract over-erasing effects that become more pronounced in highly integrated arrays. This localized quality adjustment allows dense packing without proportionally increasing over-erasing risks.
Solution Approach 2:
The P-type doping parameter change fundamentally resolves the over-erasing issue even in highly integrated structures. The modified electrical characteristics provide better control over charge removal processes, allowing area utilization to increase without proportionally increasing over-erasing risks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances data storage reliability and processing speed by ensuring no leakage current during programming and erasing, with a clear threshold voltage difference for data read operations, thus improving overall memory unit performance and integration.
Implementation Method 1
a charge storage structure (112) disposed between each of the plurality of gate layers and the annular channel pillar
Implementation Method 2
ensuring no leakage current during programming and erasing
Data Source
AI summary
Disclosed is 3D flash memory comprises a gate stack structure, an annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base, and comprising a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrating through the gate stack structure. The first source/drain pillar and the second source/drain pillar, disposed on the dielectric base, located within the annular channel pillar and penetrating through the gate stack structure, wherein the first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the annular channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the annular channel pillar. The first source/drain pillar and the second source/drain pillar are P-type doped.