3D Flash Memory With Segmented Intermediate Wiring Layers
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Solution Overview
Problem
Existing three-dimensional flash memory technologies face issues with decreased cell current and cell degradation due to increased channel layer length, leading to performance degradation.
Innovation Solution
Incorporating at least one reconfigurable intermediate wiring layer that can function as either a source or drain electrode, allowing adaptive usage and optimizing the extended lengths of upper, intermediate, and lower wiring layers to improve cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel layer length is increased to achieve three-dimensional vertical stacking, then integration density is improved, but cell current decreases and cell degradation occurs
Solution Approach 1:
The patent divides the single long channel layer into multiple shorter channel layers by introducing intermediate wiring layers at different heights. Each channel layer segment is controlled by its own word line, allowing the channel to be segmented vertically. This segmentation reduces the effective length of each channel segment, thereby improving cell current while maintaining the overall three-dimensional stacked structure for high integration density.
Solution Approach 2:
The patent introduces intermediate wiring layers as intermediary structures between the upper and lower source-drain lines. These intermediate wiring layers serve as mediators that provide additional charge storage nodes (NSC, NC, NSC) at different heights, enabling the channel to be divided into multiple segments. The intermediary structures facilitate better charge control and reduce the degradation effect of the extended channel length.
2Quantity of substance
If the channel layer length is increased for vertical stacking, then memory capacity is improved, but cell degradation increases
Solution Approach 1:
The channel layer is segmented into multiple shorter sections by introducing intermediate wiring layers at different vertical positions. Each segment is independently controlled by corresponding word lines, which allows the memory capacity to be distributed across multiple smaller charge storage regions rather than one long continuous region, thereby reducing degradation while maintaining total capacity.
Solution Approach 2:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertical stacked structure by adding intermediate wiring layers at different heights. This dimensional change allows the channel to be divided into multiple vertical segments, with each segment providing charge storage capability. The three-dimensional arrangement increases memory capacity while the segmented vertical structure mitigates degradation effects.
3Reliability
If intermediate wiring layers are added to segment the channel, then cell current is improved, but device complexity increases
Solution Approach 1:
The intermediate wiring layers serve multiple functions simultaneously: they act as charge storage nodes (NSC, NC, NSC), provide segmentation for the channel, and serve as control points for multiple word lines. This multi-functionality reduces the need for separate dedicated structures for each function, thereby improving cell current while limiting the increase in overall device complexity.
Solution Approach 2:
The patent merges the functions of charge storage and channel segmentation into the same intermediate wiring layers. Rather than having separate charge storage structures and segmentation structures, the intermediate wiring layers perform both roles, and are further merged with the word line control structure. This consolidation improves cell current through proper segmentation while avoiding the complexity of entirely separate systems.
Data Source
AI summary
A three dimensional flash memory element with middle source-drain line and manufacturing method thereof. The three dimensional flash memory element includes a string including a channel layer extended in one direction and a plurality of electrode layers vertically layered for the channel layer; an upper wiring layer placed at the top of the string; at least one intermediate wiring layer placed between the plurality of electrode layers in the intermediate area of the string; and a lower wiring layer placed at the bottom of the string. Each of the upper wiring layer, the at least one intermediate wiring layer, and the lower wiring layer is adaptively used as any one of a drain electrode or a source electrode.