3D Flash Memory Parity Super Blocks for Data Integrity
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Solution Overview
Problem
Conventional 3D NAND-type flash memory technologies face challenges in data integrity and accuracy due to complex manufacturing structures and shared control circuits, leading to data errors during programming and reading, which are not effectively addressed by existing error correction mechanisms.
Innovation Solution
Implementing a RAID-like error correction mechanism that encodes data to generate parity check codes and stores them in separate super blocks of 3D NAND-type flash memory modules, utilizing a flash memory controller with a microprocessor and codec to manage data access and error correction without increasing flash memory or buffer space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction mechanisms are used in 3D NAND-type flash memory, then data errors can be corrected, but the circuit costs increase and more memory space is occupied
Solution Approach 1:
The patent segments the flash memory into multiple super blocks, with dedicated SLC super blocks for storing parity check codes and MLC super blocks for storing data. This segmentation allows independent error correction processing without requiring complex circuitry across the entire memory structure, reducing overall circuit complexity while maintaining data integrity.
Solution Approach 2:
The patent introduces SLC super blocks as intermediary storage units that hold parity check codes separately from the data stored in MLC super blocks. This intermediary structure enables error correction functionality without directly complicating the main data storage circuits, as the parity codes are generated and stored in dedicated buffer memory and SLC blocks.
2Reliability
If conventional error correction mechanisms are used in 3D NAND-type flash memory, then data errors can be corrected, but more flash memory space and buffer memory space are occupied
Solution Approach 1:
The patent performs preliminary encoding of data to generate parity check codes before writing data to MLC super blocks. The parity codes are pre-stored in SLC super blocks, which are then used during error correction operations. This preliminary action eliminates the need to allocate additional space within the data storage blocks for error correction codes, as the correction codes are prepared and stored in advance in dedicated structures.
Solution Approach 2:
The patent creates a copy of the parity check information in SLC super blocks that serves as a reference for error correction. Instead of storing redundant error correction data alongside every data block, the system creates separate parity copies that can be used to reconstruct and verify data integrity, significantly reducing the space overhead compared to traditional distributed error correction codes.
3Device complexity
If multiple word lines share the same control circuit, then circuit costs are reduced, but data errors occur at floating gate transistors on other word lines when program fail or word line defects occur
Solution Approach 1:
The patent segments the memory into multiple independent super blocks with separate control pathways. Each super block can be independently managed and error-corrected, so that defects or program failures in one super block do not propagate to other super blocks sharing the same control circuit, thereby maintaining data integrity while preserving circuit cost efficiency.
Solution Approach 2:
The patent implements a feedback mechanism where parity check codes stored in SLC super blocks are used to detect and correct errors in MLC super blocks. When data is read from MLC super blocks, the system retrieves corresponding parity codes from SLC super blocks, performs error checking, and corrects any detected errors, providing continuous feedback-based error correction without requiring additional control circuits.
Data Source
AI summary
A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.