3D AND Flash Memory Pillar Layout for Smaller Chip Area
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Solution Overview
Problem
Current 3D memory devices face challenges in reducing chip area and simplifying wiring complexity, which are essential for high integration and efficient operation.
Innovation Solution
A three-dimensional AND flash memory device is designed with a gate stack structure and slit configuration, featuring alternately stacked gate and insulating layers, channel pillars, charge storage structures, and conductive pillars. The conductive pillars are arranged in pairs, forming an acute angle with the slit, allowing for reduced chip area and simplified wiring through multi-layer conductive interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional 3D memory device layouts are used, then the memory device can be fabricated with standard processes, but the chip area occupied is large and wiring complexity is high
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional vertical architecture by stacking multiple layers of memory cells, word lines, and bit lines in the vertical dimension. This dimensional change allows significantly higher storage density within the same chip footprint, directly reducing the occupied chip area while maintaining or improving functionality.
Solution Approach 2:
The memory device is divided into multiple sub-blocks separated by slits, with each sub-block containing independently addressable memory cells, word lines, and bit lines. This segmentation enables modular fabrication, simplified wiring within each sub-block, and independent operation of memory regions, thereby reducing overall wiring complexity while maintaining high integration.
2Quantity of substance
If more memory cells are integrated in the same chip area, then storage capacity increases, but wiring complexity and fabrication difficulty increase
Solution Approach 1:
By stacking memory cells vertically across multiple layers rather than expanding horizontally, the patent achieves higher storage capacity within the same chip area. The vertical stacking of channel structures, charge storage layers, and conductive layers multiplies the number of storable bits without proportionally increasing wiring complexity, as the same interconnect patterns can be replicated across layers.
Solution Approach 2:
The patent employs universal interconnect structures where word lines and bit lines serve multiple memory cells across different layers and sub-blocks. This multi-functional wiring approach reduces the total number of unique interconnects needed, simplifying the overall wiring complexity while supporting high storage capacity through efficient resource sharing.
3Productivity
If conventional memory architectures are used, then fabrication processes are standardized, but chip area efficiency and operation speed are limited
Solution Approach 1:
The vertical three-dimensional architecture reduces the physical distance between memory cells and access transistors, enabling faster signal propagation and shorter access times. The stacked configuration allows parallel access to multiple memory layers, improving operation speed while maintaining a compact chip footprint, thus achieving high productivity without sacrificing area efficiency.
Solution Approach 2:
The patent implements dynamic control mechanisms including selective word line activation, bit line switching, and charge trapping/detrapping in the charge storage layer to enable rapid data access and manipulation. These dynamic operations allow fast read/write cycles and improve overall operation speed while the compact vertical structure maintains area efficiency.
Data Source
AI summary
A three-dimensional AND flash memory device includes a gate stack structure and a silt. The silt extends along a first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes a plurality of rows, and each row includes a plurality of channel pillars, a plurality of charge storage structures, and a plurality of pairs of conductive pillars. The plurality of pairs of conductive pillars are arranged in the plurality of channel pillars and penetrate the gate stack structure, and are respectively connected to the plurality of channel pillars. Each pair of conductive pillars includes a first conductive pillar and a second conductive pillar separated from each other along a second direction. There is an acute angle between the second direction and the first direction.