3D Flash Memory Stack With Separate Erase Path for Longer Life
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Solution Overview
Problem
The performance of the tunnel dielectric layer in 3D flash memory deteriorates due to repeated data storage and erasure processes, reducing its effectiveness.
Innovation Solution
A semiconductor structure is designed with a novel stack configuration that includes a floating gate layer, blocking layer, tunnel dielectric layer, channel layer, and erasing layer, where electrons move along a different path during erasure to minimize tunnel dielectric layer dissipation, using conductive erasing layers and insulating materials to extend the semiconductor's lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electrons move between floating gate and channel layer through tunnel dielectric layer during repeated storing and erasing, then data storage and erasure function is achieved, but tunnel dielectric layer performance deteriorates
Solution Approach 1:
The patent segments the electron transport path by introducing an erasing layer that provides an alternative erasure path for electrons, separating the storage path (through tunnel dielectric) from the erasure path (through erasing layer), thereby reducing cumulative damage to the tunnel dielectric layer
Solution Approach 2:
The erasing layer acts as an intermediary structure that facilitates electron removal from the floating gate during erasure operations, providing a dedicated pathway that spares the tunnel dielectric layer from repeated stress
2Duration of action of moving object
If tunnel dielectric layer is used for repeated electron transport, then data writing and erasing operations are enabled, but tunnel dielectric layer dissipates and functionality reduces
Solution Approach 1:
The patent divides the electron transport functionality into separate layers: the tunnel dielectric layer handles electron injection during programming, while the erasing layer handles electron removal during erasure, extending the operational lifespan of both structures
Solution Approach 2:
The erasing layer is预先 introduced as a protective measure to cushion the tunnel dielectric layer from repeated erasure stress, preventing premature failure and maintaining long-term reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the dissipation of the tunnel dielectric layer, thereby extending the life and performance of the semiconductor by minimizing wear and tear during repeated data writing and erasure cycles.
Implementation Method 1
electrons move between the floating gate and a channel layer by passing through a tunnel dielectric layer
Data Source
AI summary
A semiconductor with 3D flash memory storing cells giving an extended life time includes a stack structure in each storing cell, a receiving space crossing through the stack structure, a blocking layer, at least one floating gate layer, and a channel layer. The stack structure includes at least one control gate layer, at least two dielectric layers, and at least one erasing layer. The receiving space comprises a first receiving portion communicating with several second receiving portions. The first receiving portion crosses through the stack structure and the second receiving portions are coplanar with the control gate layer. The blocking layer insulates the floating gate layer from the control gate layers. The erasing layer and floating gate layer form a passageway for electrons when data erasure is required in the semiconductor. A method for fabricating the semiconductor is also disclosed.