3D Split-Gate Flash Memory Cell for Speed-Density Trade-Off
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Solution Overview
Problem
Current NOR flash memory devices with stacked-gate structures have slow programming and erasing speeds, while split-gate flash memory devices compromise integration density, creating a trade-off between operation speed and integration density.
Innovation Solution
A 3D flash memory device with a split-gate structure that includes a channel structure, first and second gates, a storage structure, and source and bit line pillars, where the first gate does not vertically overlap with the channel structure, allowing for improved integration density and operation speed through a stacked configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If split-gate flash memory structure is used, then programming and erasing speeds are improved, but cell size increases and integration density decreases
Solution Approach 1:
The patent transitions from a planar 2D flash memory structure to a three-dimensional stacked structure. The channel structure extends vertically through multiple memory layers, with first and second gates positioned at different vertical levels. This 3D configuration enables split-gate functionality while reducing the lateral footprint of each cell, thereby improving integration density without sacrificing programming and erasing speeds.
Solution Approach 2:
The patent implements a nested structure where the channel structure is surrounded by storage structures (such as charge trapping layers or tunnel insulators) at multiple vertical levels. The first gate and second gate are positioned at different heights, creating a nested spatial arrangement that enables efficient charge injection and extraction paths while minimizing the horizontal cell area.
2Area of stationary object
If stacked-gate structure is used, then integration density is improved, but programming and erasing speeds deteriorate
Solution Approach 1:
The gate structure is segmented into two separate gates (first gate and second gate) positioned at different vertical levels rather than stacking multiple gates horizontally. This segmentation creates distinct control regions that enable efficient charge injection from one gate and extraction at the other, maintaining fast programming and erasing speeds while achieving compact vertical integration.
Solution Approach 2:
Instead of stacking gates in the horizontal plane, the patent positions gates along the vertical dimension. The channel structure extends vertically, with gates located at different heights, transforming the gate arrangement from a 2D planar configuration to a 3D vertical configuration. This enables both compact cell size and efficient charge transport paths for high-speed operation.
Data Source
AI summary
A flash memory cell includes a channel structure, a first gate, a second gate, a storage structure, a source line pillar and a bit line pillar. The channel structure is formed over a substrate. The first gate is formed adjacent to the channel structure. The second gate is separated from the first gate and the channel structure. The storage structure is adjacent to the channel structure. The source line pillar and the bit line pillar are respectively adjacent to opposite sidewalls of the channel structure. The first gate does not vertically overlap with the channel structure.