3D Flash Memory Voltage Distribution Control for QLC Reliability
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Solution Overview
Problem
Conventional 3D flash memory technologies face challenges in implementing multi-levels beyond quad-level cell (QLC) methods and suffer from deteriorating memory reliability due to abnormal shapes in vertical channel structures, leading to accelerated pass voltage disturbances and reduced channel current during program and read operations.
Innovation Solution
A method and system for circuit compensation that secures a threshold voltage distribution region by narrowing erase threshold voltage distributions and sets multi-level program threshold voltages, while monitoring and controlling voltages applied to memory cells with abnormal shapes to match those without abnormalities, thereby improving cell characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional QLC method is used to implement multi-levels, then 16 states of 4 bits can be stored in one memory cell, but it is difficult to implement multi-level better than QLC method due to limitations of current cell operation technology
Solution Approach 1:
The patent transitions from conventional planar flash memory to 3D vertical channel structure flash memory, utilizing the vertical dimension to achieve higher integration. The vertical channel structures extend in the third direction perpendicular to the substrate, enabling multi-level implementation beyond QLC by adding spatial dimensionality to the storage architecture.
Solution Approach 2:
The patent employs parameter changes by adjusting threshold voltage distributions through controlled erase operations. By narrowing the erase threshold voltage distribution and setting multi-level program threshold voltages, the system achieves better multi-level implementation capability, enabling more than 16 states per memory cell.
2Productivity
If vertical channel structure is advanced in conventional 3D flash memory, then integration is improved, but abnormal shapes such as spikes occur causing changes in memory cell characteristics and deteriorating memory reliability
Solution Approach 1:
The patent performs preliminary actions by conducting erase operations before program operations to narrow the threshold voltage distribution. This preliminary erase step ensures that memory cells are properly prepared, reducing the likelihood of abnormal shape formation and associated reliability issues while maintaining high integration density.
Solution Approach 2:
The patent implements feedback mechanisms through verify operations that monitor threshold voltage distributions. By continuously checking and adjusting voltages based on measured characteristics, the system compensates for variations and prevents abnormal shape development, thereby maintaining reliability in advanced 3D structures.
3Productivity
If vertical channel structure is advanced in conventional 3D flash memory, then integration is improved, but pass voltage disturbances are accelerated during program and read operations
Solution Approach 1:
The patent applies preliminary erase operations to narrow threshold voltage distributions before program operations. This preliminary preparation reduces the voltage window required for subsequent operations, thereby minimizing pass voltage disturbances during program and read operations while maintaining high integration density.
Solution Approach 2:
The patent changes voltage parameters dynamically by adjusting program and read voltages based on the narrowed threshold voltage distribution. This parameter optimization reduces the magnitude of pass voltage disturbances, preventing harmful effects in advanced 3D flash memory structures.
4Productivity
If vertical channel structure is advanced in conventional 3D flash memory, then integration is improved, but channel current is reduced
Solution Approach 1:
The patent performs preliminary erase operations to narrow threshold voltage distributions, which optimizes the electrical characteristics of vertical channel structures. This preliminary preparation improves channel current flow by ensuring proper voltage alignment, counteracting the current reduction effect of high integration density.
Solution Approach 2:
The patent adjusts voltage parameters to compensate for channel current reduction in highly integrated structures. By optimizing program and read voltages based on narrowed threshold distributions, the system maintains adequate channel current levels despite increased integration density.
Data Source
AI summary
Disclosed are a 3D flash memory and an operating method thereof.