3D Flip-Flop Clock Skew Reduction via Monolithic Intertier Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D integrated circuits (ICs) face challenges in minimizing clock skew and power consumption due to high resistance-capacitance (RC) factors in through silicon vias (TSVs) and the need for asynchronous operation with separate clocks, which is not viable for low-power circuit designs requiring synchronous operation.
Innovation Solution
Implementing a single clock source distributed across tiers of a 3D IC using selectively controllable flip-flops, with a master latch on one tier and a slave latch on another, connected by monolithic intertier vias (MIVs) to provide synchronous operation and reduce clock skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) are used to distribute clock signals across tiers, then clock signal distribution is achieved, but high RC factor causes increased clock skew and power consumption
Solution Approach 1:
The patent changes the physical parameters of the via structure by transitioning from TSVs to monolithic intertier vias (MIVs) with smaller dimensions and optimized geometry. This parameter change reduces the RC factor of the interconnect, thereby reducing both clock skew and power consumption while maintaining reliable clock signal distribution across tiers
2Reliability
If separate clocks are provided on different levels of the 3DIC, then clock skew is reduced, but asynchronous operation is forced and area penalty increases
Solution Approach 1:
The patent segments the flip-flop circuit into two separate physical locations on different tiers: the master latch on one tier and the slave latch on another tier. This segmentation allows the use of a single clock source distributed across tiers while maintaining synchronous operation, avoiding the need for multiple separate clock sources and their associated area penalties
3Device complexity
If a single clock source is used for all tiers, then area is conserved, but high RC factor in TSVs causes unacceptable clock skew
Solution Approach 1:
The patent changes the physical parameters of the intertier connections by using MIVs instead of TSVs. The MIVs have smaller dimensions and lower RC characteristics, enabling a single clock source to be distributed across tiers with acceptable clock skew, thus maintaining area efficiency without sacrificing timing reliability
4Ease of manufacture
If flip-flops are placed entirely on one tier, then manufacturing is simplified, but clock skew between tiers increases
Solution Approach 1:
The patent segments the flip-flop across tier boundaries, with the master latch on one tier and the slave latch on another tier connected by MIVs. This segmentation reduces the clock path length across tiers and minimizes inter-tier clock skew, while the modular design maintains manufacturing feasibility through standard 3D IC processes
Data Source
AI summary
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.