3D Floating-Body DRAM Cell Architecture for High Density
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Solution Overview
Problem
Current technologies have not successfully implemented a cost-effective three-dimensional (3D) array structure for dynamic random-access memory (DRAM) due to its one-transistor-one-capacitor (1T1C) cell structure, limiting the realization of ultra-high-density DRAM.
Innovation Solution
A novel 3D array structure using floating-body cells is developed, similar to 3D NAND flash memory, with a deep trench process, incorporating a bit line, source line, front gate, back gate, and a floating body with specific voltage modulation to enhance channel current sensing, enabling enlarged current sensing windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D array structure is used to increase memory capacity, then memory density is improved, but the one-transistor-one-capacitor (1T1C) cell structure makes it difficult to realize cost-effective DRAM
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional 3D vertical architecture, stacking multiple memory cell layers vertically to increase storage capacity per unit area. This dimensional change enables ultra-high-density memory while maintaining compatibility with standard semiconductor manufacturing processes through deep trench formation and layered deposition.
Solution Approach 2:
The floating-body cell structure serves multiple functions: it acts as both the storage element and the sensing element, eliminating the need for separate capacitor and transistor components required in traditional 1T1C DRAM. This multi-functionality simplifies the cell structure while enabling 3D vertical stacking for increased capacity.
2Ease of operation
If traditional 1T1C DRAM structure is used, then memory operation is simple, but ultra-high-density 3D array structure cannot be realized
Solution Approach 1:
The patent modifies the electrical parameters and physical dimensions of the memory cell, transitioning from lateral planar geometry to vertical three-dimensional geometry. The deep trench structure and vertical channel formation enable higher density while the floating-body mechanism maintains relatively simple read/write operations through voltage modulation.
3Measurement precision
If floating-body cells with voltage modulation are used, then current sensing window is enlarged, but device structure becomes more complex
Solution Approach 1:
The floating-body cell structure utilizes its own internal physics - the body effect and threshold voltage modulation - to provide enhanced sensing capability. The floating body automatically modulates the channel current based on stored charge, eliminating the need for external sensing circuitry or additional components, thus achieving high measurement precision without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the realization of ultra-high-density DRAM by providing an enlarged current sensing window, improving memory capacity and accuracy, and reducing the complexity of word line decoders.
Implementation Method 1
a floating body semiconductor material having an internal side surface that surrounds and connects to the bit line... When the cell is in a data 0 state and selected voltages are supplied to the bit line, the source line, and the front gate and a negative voltage is supplied to the back gate, channel current between the bit line and the source line flows at a first level
Data Source
AI summary
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a cell structure includes a bit line, source line, front gate, and back gate. The cell structure also includes a floating body having surfaces coupled to the bit line, source line, front gate, and back gate. The floating body has a selected thickness between the front gate and the back gate. When the cell is in a data 0 state and selected voltages are supplied to the bit line, the source line, and the front gate and a negative voltage is supplied to the back gate, channel current between the bit line and the source line flows at a first level. When the cell is in a data 1 state, the channel current between the bit line and the source line flows at a second level to provide an enlarged current sensing window.