3D Floating Body Memory Layout for Higher Density Scaling
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Solution Overview
Problem
Conventional methods for increasing memory density in floating body memory arrays face challenges due to limitations in surface area and require complex and costly process adjustments, leading to diminishing returns in memory scaling.
Innovation Solution
The implementation of vertically stacked floating body memory designs using fewer masks and at a lower cost, incorporating either vertical or horizontal transistors to increase active memory layers, allowing for higher density without significant process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional methods are used to increase memory density, then memory density improves, but surface area limitations and process complexity increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory layers are stacked above each other, utilizing the vertical dimension to increase memory density without proportionally increasing footprint area or process complexity. This dimensional change allows more memory cells to be packed into the same substrate area.
2Quantity of substance
If memory scaling is pursued using conventional approaches, then memory density increases, but cost and process adjustments become more complex
Solution Approach 1:
The memory structure is segmented into multiple identical stacked layers, each containing complete memory cell functionality. These standardized modules can be fabricated using repeated process cycles, improving manufacturing efficiency and reducing per-unit cost compared to conventional scaling approaches that require increasingly complex custom process adjustments.
3Quantity of substance
If vertically stacked memory designs are implemented, then memory cell density increases, but fabrication process complexity may increase
Solution Approach 1:
The patent uses identical copies of the same memory cell structure stacked vertically. Each layer is a replicate of the others, allowing standardized fabrication processes to be repeated across multiple layers. This copying approach simplifies fabrication compared to creating unique structures for each memory layer, as the same process recipes and equipment settings can be reused.
Data Source
AI summary
Integrated circuit (IC) devices implementing three-dimensional (3D) floating body memory are disclosed. An example IC device includes a floating body memory cell comprising a transistor having a first source or drain (S/D) region, a second S/D region, and a gate over a channel portion between the first and second S/D regions; a BL coupled to the first S/D region and parallel to a first axis of a Cartesian coordinate system; a SL coupled to the second S/D region and parallel to a second axis of the coordinate system; and a WL coupled to or being a part of the gate and parallel to a third axis of the coordinate system. IC devices implementing 3D floating body memory as described herein may be used to address the scaling challenges of conventional memory technologies and enable high-density embedded memory compatible with advanced CMOS processes.