3D Floating Gate NAND Memory Vertical Stacking
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Solution Overview
Problem
Current NAND flash memory technologies face challenges in achieving lower costs and larger capacities, which can be addressed by utilizing three-dimensional NAND memory structures.
Innovation Solution
The development of memory arrays with specific configurations, including parallel and vertically stacked memory cells, each comprising a channel, insulators, and a control gate, along with vertical and horizontal isolation structures, and methods for their fabrication, such as depositing bilayer stacks and etching voids to form and position these components effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional NAND memory structures are utilized, then storage density and capacity are improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked along the vertical axis, with each cell comprising channel, floating gate, and control gate structures arranged in three dimensions. This dimensional transition enables significantly higher storage density by utilizing vertical space rather than only horizontal plane area.
Solution Approach 2:
The memory cell structures are nested within vertical stacks, with insulating materials and conductive structures nested within each other. The floating gate is positioned between the channel and control gate, creating a nested configuration where each component is contained within the structural envelope of the cell stack, maximizing space utilization.
2Quantity of substance
If memory cells are positioned parallel to each other in vertical stacks, then storage capacity increases, but interference between floating gates increases
Solution Approach 1:
Insulating materials are positioned between adjacent floating gates in the vertical stack to act as intermediaries that electrically isolate each floating gate from its neighbors. This prevents unwanted electrical interference and capacitive coupling between floating gates of different memory cells while maintaining the compact vertical stack configuration.
Solution Approach 2:
The patent applies different materials with specific local properties to different regions of the memory cell stack. Insulating materials are selectively positioned in specific locations between floating gates and channels to provide localized electrical isolation where needed, while maintaining conductive pathways where required for memory operation.
3Manufacturing precision
If bilayer stacks of insulating and floating gate materials are deposited, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The fabrication process segments the deposition into distinct sequential steps: first depositing insulating material layers, then floating gate material layers, with intermediate etching and processing steps. This segmentation allows precise control over the thickness, composition, and positioning of each material layer independently, achieving high manufacturing precision through controlled sequential deposition rather than attempting to deposit complex multi-material structures in a single step.
Data Source
AI summary
Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.