3D Forksheet CMOS Stacking for Higher Transistor Density
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Solution Overview
Problem
The existing methods for reducing the area occupied by transistors in integrated circuits are limited by the minimum side-to-side spacing distance, leading to wasted space on IC chips, as they rely on horizontal area reduction rather than efficient vertical stacking and semiconductor type utilization.
Innovation Solution
The implementation of three-dimensional dual complementary circuit structures, where a first forksheet structure is stacked on a second forksheet structure with a dividing wall, bisecting semiconductor slabs into portions of different semiconductor types to form two complementary metal-oxide semiconductor (CMOS) circuits in a smaller area, thereby increasing circuit density and reducing the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are reduced in horizontal size, then more transistors can fit on a chip, but the minimum side-to-side spacing distance required by fabrication processes causes significant area waste
Solution Approach 1:
The patent transitions from two-dimensional planar transistor layouts to three-dimensional vertically stacked configurations. Multiple transistor channels are stacked vertically within a single footprint, allowing more transistors to be packed into the same chip area without requiring additional horizontal spacing, thus resolving the contradiction between transistor density and chip area utilization
Solution Approach 2:
The patent merges multiple transistor channels into a single integrated vertical structure where n-type and p-type channels are interleaved and share common source/drain regions and gating structures. This merging eliminates redundant spacing between separate transistor devices while maintaining electrical isolation through the alternating semiconductor type arrangement
2Ease of manufacture
If separate circuit device structures are used for each transistor, then fabrication is simpler, but the area occupied by minimum spacing between structures is wasted
Solution Approach 1:
Multiple transistor channels are merged into a single integrated structure with shared source/drain regions and gating, eliminating the need for separate fabrication processes for each transistor while maintaining electrical isolation through alternating semiconductor types
Solution Approach 2:
The unified structure is segmented into alternating n-type and p-type channel regions that are electrically isolated from each other, allowing independent transistor operation within the merged structure while simplifying fabrication through a single integrated process
Data Source
AI summary
A 3D dual complementary-circuit structure includes a first forksheet structure stacked on a first side of, in a first direction, a second forksheet structure to provide two complementary circuits in a space of a single forksheet structure. A dividing wall bisects at least one semiconductor slab in the first forksheet structure into a first slab portion with a first semiconductor type and a second slab portion with a second semiconductor type and also bisects at least one semiconductor slab in the second forksheet structure into a third slab portion with a third semiconductor type and a fourth slab portion with a fourth semiconductor type. One of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type may be a same semiconductor type as the first semiconductor type. Two complementary metal oxide semiconductor (CMOS) circuits may be formed in the area of a single forksheet structure.